JAJSSK1 December   2023 AM62P , AM62P-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
    1. 3.1 機能ブロック図
  5. 4 Device Comparison
    1. 4.1 Related Products
  6. 5 Terminal Configuration and Functions
    1. 5.1 Pin Diagrams
    2. 5.2 Pin Attributes
      1.      11
      2.      12
    3. 5.3 Signal Descriptions
      1.      14
      2. 5.3.1  CPSW3G
        1. 5.3.1.1 MAIN Domain
          1.        17
          2.        18
          3.        19
          4.        20
      3. 5.3.2  CPTS
        1. 5.3.2.1 MAIN Domain
          1.        23
      4. 5.3.3  CSI-2
        1. 5.3.3.1 MAIN Domain
          1.        26
      5. 5.3.4  DDRSS
        1. 5.3.4.1 MAIN Domain
          1.        29
      6. 5.3.5  DSI
        1. 5.3.5.1 MAIN Domain
          1.        32
      7. 5.3.6  DSS
        1. 5.3.6.1 MAIN Domain
          1.        35
      8. 5.3.7  ECAP
        1. 5.3.7.1 MAIN Domain
          1.        38
          2.        39
          3.        40
      9. 5.3.8  Emulation and Debug
        1. 5.3.8.1 MAIN Domain
          1.        43
        2. 5.3.8.2 MCU Domain
          1.        45
      10. 5.3.9  EPWM
        1. 5.3.9.1 MAIN Domain
          1.        48
          2.        49
          3.        50
          4.        51
      11. 5.3.10 EQEP
        1. 5.3.10.1 MAIN Domain
          1.        54
          2.        55
          3.        56
      12. 5.3.11 GPIO
        1. 5.3.11.1 MAIN Domain
          1.        59
          2.        60
        2. 5.3.11.2 MCU Domain
          1.        62
      13. 5.3.12 GPMC
        1. 5.3.12.1 MAIN Domain
          1.        65
      14. 5.3.13 I2C
        1. 5.3.13.1 MAIN Domain
          1.        68
          2.        69
          3.        70
          4.        71
        2. 5.3.13.2 MCU Domain
          1.        73
        3. 5.3.13.3 WKUP Domain
          1.        75
      15. 5.3.14 MCAN
        1. 5.3.14.1 MAIN Domain
          1.        78
          2.        79
        2. 5.3.14.2 MCU Domain
          1.        81
          2.        82
      16. 5.3.15 MCASP
        1. 5.3.15.1 MAIN Domain
          1.        85
          2.        86
          3.        87
      17. 5.3.16 MCSPI
        1. 5.3.16.1 MAIN Domain
          1.        90
          2.        91
          3.        92
        2. 5.3.16.2 MCU Domain
          1.        94
          2.        95
      18. 5.3.17 MDIO
        1. 5.3.17.1 MAIN Domain
          1.        98
      19. 5.3.18 MMC
        1. 5.3.18.1 MAIN Domain
          1.        101
          2.        102
          3.        103
      20. 5.3.19 OLDI
        1. 5.3.19.1 MAIN Domain
          1.        106
      21. 5.3.20 OSPI
        1. 5.3.20.1 MAIN Domain
          1.        109
      22. 5.3.21 Power Supply
        1.       111
      23. 5.3.22 Reserved
        1.       113
      24. 5.3.23 System and Miscellaneous
        1. 5.3.23.1 Boot Mode Configuration
          1. 5.3.23.1.1 MAIN Domain
            1.         117
        2. 5.3.23.2 Clock
          1. 5.3.23.2.1 MCU Domain
            1.         120
          2. 5.3.23.2.2 WKUP Domain
            1.         122
        3. 5.3.23.3 System
          1. 5.3.23.3.1 MAIN Domain
            1.         125
          2. 5.3.23.3.2 MCU Domain
            1.         127
          3. 5.3.23.3.3 WKUP Domain
            1.         129
        4. 5.3.23.4 VMON
          1.        131
      25. 5.3.24 TIMER
        1. 5.3.24.1 MAIN Domain
          1.        134
        2. 5.3.24.2 MCU Domain
          1.        136
        3. 5.3.24.3 WKUP Domain
          1.        138
      26. 5.3.25 UART
        1. 5.3.25.1 MAIN Domain
          1.        141
          2.        142
          3.        143
          4.        144
          5.        145
          6.        146
          7.        147
        2. 5.3.25.2 MCU Domain
          1.        149
        3. 5.3.25.3 WKUP Domain
          1.        151
      27. 5.3.26 USB
        1. 5.3.26.1 MAIN Domain
          1.        154
          2.        155
    4. 5.4 Pin Connectivity Requirements
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings for Devices which are not AEC - Q100 Qualified
    3. 6.3  ESD Ratings for AEC - Q100 Qualified Devices
    4. 6.4  Power-On Hours (POH)
    5. 6.5  Recommended Operating Conditions
    6. 6.6  Operating Performance Points
    7. 6.7  Power Consumption Summary
    8. 6.8  Electrical Characteristics
      1. 6.8.1  I2C Open-Drain, and Fail-Safe (I2C OD FS) Electrical Characteristics
      2. 6.8.2  Fail-Safe Reset (FS RESET) Electrical Characteristics
      3. 6.8.3  High-Frequency Oscillator (HFOSC) Electrical Characteristics
      4. 6.8.4  Low-Frequency Oscillator (LFXOSC) Electrical Characteristics
      5. 6.8.5  eMMCPHY Electrical Characteristics
      6. 6.8.6  SDIO Electrical Characteristics
      7. 6.8.7  LVCMOS Electrical Characteristics
      8. 6.8.8  OLDI LVDS (OLDI) Electrical Characteristics
      9. 6.8.9  CSI-2 (D-PHY) Electrical Characteristics
      10. 6.8.10 DSI (D-PHY) Electrical Characteristics
      11. 6.8.11 USB2PHY Electrical Characteristics
      12. 6.8.12 DDR Electrical Characteristics
    9. 6.9  VPP Specifications for One-Time Programmable (OTP) eFuses
      1. 6.9.1 Recommended Operating Conditions for OTP eFuse Programming
      2. 6.9.2 Hardware Requirements
      3. 6.9.3 Programming Sequence
      4. 6.9.4 Impact to Your Hardware Warranty
    10. 6.10 Thermal Resistance Characteristics
      1. 6.10.1 Thermal Resistance Characteristics for AMH Package
    11. 6.11 Timing and Switching Characteristics
      1. 6.11.1 Timing Parameters and Information
      2. 6.11.2 Power Supply Requirements
        1. 6.11.2.1 Power Supply Slew Rate Requirement
        2. 6.11.2.2 Power Supply Sequencing
          1. 6.11.2.2.1 Power-Up Sequencing
          2. 6.11.2.2.2 Power-Down Sequencing
          3. 6.11.2.2.3 Partial IO Power Sequencing
      3. 6.11.3 System Timing
        1. 6.11.3.1 Reset Timing
        2. 6.11.3.2 Error Signal Timing
        3. 6.11.3.3 Clock Timing
      4. 6.11.4 Clock Specifications
        1. 6.11.4.1 Input Clocks / Oscillators
          1. 6.11.4.1.1 MCU_OSC0 Internal Oscillator Clock Source
            1. 6.11.4.1.1.1 Load Capacitance
            2. 6.11.4.1.1.2 Shunt Capacitance
          2. 6.11.4.1.2 MCU_OSC0 LVCMOS Digital Clock Source
          3. 6.11.4.1.3 WKUP_LFOSC0 Internal Oscillator Clock Source
          4. 6.11.4.1.4 WKUP_LFOSC0 LVCMOS Digital Clock Source
          5. 6.11.4.1.5 WKUP_LFOSC0 Not Used
        2. 6.11.4.2 Output Clocks
        3. 6.11.4.3 PLLs
        4. 6.11.4.4 Recommended System Precautions for Clock and Control Signal Transitions
      5. 6.11.5 Peripherals
        1. 6.11.5.1  CPSW3G
          1. 6.11.5.1.1 CPSW3G MDIO Timing
          2. 6.11.5.1.2 CPSW3G RMII Timing
          3. 6.11.5.1.3 CPSW3G RGMII Timing
        2. 6.11.5.2  CPTS
        3. 6.11.5.3  CSI-2
        4. 6.11.5.4  DDRSS
        5. 6.11.5.5  DSI
        6. 6.11.5.6  DSS
        7. 6.11.5.7  ECAP
        8. 6.11.5.8  Emulation and Debug
          1. 6.11.5.8.1 Trace
          2. 6.11.5.8.2 JTAG
        9. 6.11.5.9  EPWM
        10. 6.11.5.10 EQEP
        11. 6.11.5.11 GPIO
        12. 6.11.5.12 GPMC
          1. 6.11.5.12.1 GPMC and NOR Flash — Synchronous Mode
          2. 6.11.5.12.2 GPMC and NOR Flash — Asynchronous Mode
          3. 6.11.5.12.3 GPMC and NAND Flash — Asynchronous Mode
        13. 6.11.5.13 I2C
        14. 6.11.5.14 MCAN
        15. 6.11.5.15 MCASP
        16. 6.11.5.16 MCSPI
          1. 6.11.5.16.1 MCSPI — Controller Mode
          2. 6.11.5.16.2 MCSPI — Peripheral Mode
        17. 6.11.5.17 MMCSD
          1. 6.11.5.17.1 MMC0 - eMMC Interface
            1. 6.11.5.17.1.1 Legacy SDR Mode
            2. 6.11.5.17.1.2 High Speed SDR Mode
            3. 6.11.5.17.1.3 High Speed DDR Mode
            4. 6.11.5.17.1.4 HS200 Mode
            5. 6.11.5.17.1.5 HS400 Mode
          2. 6.11.5.17.2 MMC1/MMC2 - SD/SDIO Interface
            1. 6.11.5.17.2.1 Default Speed Mode
            2. 6.11.5.17.2.2 High Speed Mode
            3. 6.11.5.17.2.3 UHS–I SDR12 Mode
            4. 6.11.5.17.2.4 UHS–I SDR25 Mode
            5. 6.11.5.17.2.5 UHS–I SDR50 Mode
            6. 6.11.5.17.2.6 UHS–I DDR50 Mode
            7. 6.11.5.17.2.7 UHS–I SDR104 Mode
        18. 6.11.5.18 OLDI
          1. 6.11.5.18.1 OLDI0 Switching Characteristics
        19. 6.11.5.19 OSPI
          1. 6.11.5.19.1 OSPI0 PHY Mode
            1. 6.11.5.19.1.1 OSPI0 With PHY Data Training
            2. 6.11.5.19.1.2 OSPI0 Without Data Training
              1. 6.11.5.19.1.2.1 OSPI0 PHY SDR Timing
              2. 6.11.5.19.1.2.2 OSPI0 PHY DDR Timing
          2. 6.11.5.19.2 OSPI0 Tap Mode
            1. 6.11.5.19.2.1 OSPI0 Tap SDR Timing
            2. 6.11.5.19.2.2 OSPI0 Tap DDR Timing
        20. 6.11.5.20 Timers
        21. 6.11.5.21 UART
        22. 6.11.5.22 USB
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Processor Subsystems
      1. 7.2.1 Arm Cortex-A53 Subsystem
      2. 7.2.2 Device/Power Manager
      3. 7.2.3 MCU Arm Cortex-R5F Subsystem
    3. 7.3 Accelerators and Coprocessors
    4. 7.4 Other Subsystems
      1. 7.4.1 Dual Clock Comparator (DCC)
      2. 7.4.2 Data Movement Subsystem (DMSS)
      3. 7.4.3 Memory Cyclic Redundancy Check (MCRC)
      4. 7.4.4 Peripheral DMA Controller (PDMA)
      5. 7.4.5 Real-Time Clock (RTC)
    5. 7.5 Peripherals
      1. 7.5.1  Gigabit Ethernet Switch (CPSW3G)
      2. 7.5.2  Camera Serial Interface Receiver (CSI_RX_IF)
      3. 7.5.3  Display Subsystem (DSS)
      4. 7.5.4  Enhanced Capture (ECAP)
      5. 7.5.5  Error Location Module (ELM)
      6. 7.5.6  Enhanced Pulse Width Modulation (EPWM)
      7. 7.5.7  Error Signaling Module (ESM)
      8. 7.5.8  Enhanced Quadrature Encoder Pulse (EQEP)
      9. 7.5.9  General-Purpose Interface (GPIO)
      10. 7.5.10 General-Purpose Memory Controller (GPMC)
      11. 7.5.11 Global Timebase Counter (GTC)
      12. 7.5.12 Inter-Integrated Circuit (I2C)
      13. 7.5.13 Modular Controller Area Network (MCAN)
      14. 7.5.14 Multichannel Audio Serial Port (MCASP)
      15. 7.5.15 Multichannel Serial Peripheral Interface (MCSPI)
      16. 7.5.16 Multi-Media Card Secure Digital (MMCSD)
      17. 7.5.17 Octal Serial Peripheral Interface (OSPI)
      18. 7.5.18 Timers
      19. 7.5.19 Universal Asynchronous Receiver/Transmitter (UART)
      20. 7.5.20 Universal Serial Bus Subsystem (USBSS)
  9. 8 Applications, Implementation, and Layout
    1. 8.1 Device Connection and Layout Fundamentals
      1. 8.1.1 Power Supply
        1. 8.1.1.1 Power Supply Designs
        2. 8.1.1.2 Power Distribution Network Implementation Guidance
      2. 8.1.2 External Oscillator
      3. 8.1.3 JTAG, EMU, and TRACE
      4. 8.1.4 Unused Pins
    2. 8.2 Peripheral- and Interface-Specific Design Information
      1. 8.2.1 DDR Board Design and Layout Guidelines
      2. 8.2.2 OSPI/QSPI/SPI Board Design and Layout Guidelines
        1. 8.2.2.1 No Loopback, Internal PHY Loopback, and Internal Pad Loopback
        2. 8.2.2.2 External Board Loopback
        3. 8.2.2.3 DQS (only available in Octal SPI devices)
      3. 8.2.3 USB VBUS Design Guidelines
      4. 8.2.4 System Power Supply Monitor Design Guidelines
      5. 8.2.5 High Speed Differential Signal Routing Guidance
      6. 8.2.6 Thermal Solution Guidance
    3. 8.3 Clock Routing Guidelines
      1. 8.3.1 Oscillator Routing
  10. 9 Device and Documentation Support
    1. 9.1 Device Nomenclature
      1. 9.1.1 Standard Package Symbolization
      2. 9.1.2 Device Naming Convention
    2. 9.2 Tools and Software
    3. 9.3 Documentation Support
    4. 9.4 サポート・リソース
    5. 9.5 Trademarks
    6. 9.6 静電気放電に関する注意事項
    7. 9.7 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Packaging Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • AMH|466
サーマルパッド・メカニカル・データ
発注情報

5.4 Pin Connectivity Requirements

This section describes connectivity requirements for package balls that have specific connectivity requirements and unused package balls.

Note:

All power pins must be supplied with the voltages specified in Section 6.5, Recommended Operating Conditions, unless otherwise specified.

Note:

For additional clarification, "leave unconnected" or "no connect" (NC) means no signal traces can be connected to these device ball numbers.

Table 5-74 Connectivity Requirements
AMH
BALL
NUMBER		 BALL NAME CONNECTION REQUIREMENTS
G6
B13		 MCU_ERRORn
TRSTn		 Each of these balls must be connected to VSS through separate external pull resistors to ensure these balls are held to a valid logic low level if a PCB signal trace is connected and not actively driven by an attached device. The internal pull-down can be used to hold a valid logic low level if no PCB signal trace is connected to the ball.
B12
D13
F11
G24
C13
E13
E14		 EMU0
EMU1
MCU_RESETz
RESET_REQz
TCK
TDI
TMS		 Each of these balls must be connected to the corresponding power supply(1) through separate external pull resistors to ensure the inputs associated with these balls are held to a valid logic high level if a PCB signal trace is connected and not actively driven by an attached device. The internal pull-up can be used to hold a valid logic high level if no PCB signal trace is connected to the ball.
E11
D11
A13
C11		 MCU_I2C0_SCL
MCU_I2C0_SDA
WKUP_I2C0_SCL
WKUP_I2C0_SDA		 Each of these balls must be connected to the corresponding power supply(1) through separate external pull resistors to ensure the inputs associated with these balls are held to a valid logic high level.
U22
U21
U20
V25
T20
T21
V24
W25
AC25
AB25
AA25
W24
Y24
AD25
AB24
AC24		 GPMC0_AD0
GPMC0_AD1
GPMC0_AD2
GPMC0_AD3
GPMC0_AD4
GPMC0_AD5
GPMC0_AD6
GPMC0_AD7
GPMC0_AD8
GPMC0_AD9
GPMC0_AD10
GPMC0_AD11
GPMC0_AD12
GPMC0_AD13
GPMC0_AD14
GPMC0_AD15		 Each of these balls must be connected to the corresponding power supply(1) or VSS through separate external pull resistors to ensure the inputs associated with these balls are held to a valid logic high or low level as appropriate to select the desired device boot mode.
1G2
1H1
AE2
B1
1C1
1D2
1E1
1F1
1E2		 VDDS_DDR
VDDS_DDR
VDDS_DDR
VDDS_DDR
VDDS_DDR
VDDS_DDR
VDDS_DDR
VDDS_DDR
VDDS_DDR_C		 If DDRSS is not used, each of these balls must be connected directly to VSS.
T6
K3
T5
T1
P6
T4
K5
L2
L3
M2
N2
K2
N3
L1
M1
T2
R2
N5
P3
P2
N6
K4
Y6
U6
Y5
R1
P1
N4
P5
L6
T3
C3
H3
V4
AD1
B2
A3
A4
A5
A2
B4
D2
C4
E2
F1
G5
F2
G3
H4
J2
G2
U2
U3
U5
V5
V2
Y2
Y3
AA4
AC2
AA2
AC4
AD2
AD3
AC3
AE4
AE3
D1
C1
J1
H1
W1
V1
AA1
AB1
L5
V6
AA5		 DDR0_ACT_n
DDR0_ALERT_n
DDR0_CAS_n
DDR0_PAR
DDR0_RAS_n
DDR0_WE_n
DDR0_A0
DDR0_A1
DDR0_A2
DDR0_A3
DDR0_A4
DDR0_A5
DDR0_A6
DDR0_A7
DDR0_A8
DDR0_A9
DDR0_A10
DDR0_A11
DDR0_A12
DDR0_A13
DDR0_BA0
DDR0_BA1
DDR0_BG0
DDR0_BG1
DDR0_CAL0
DDR0_CK0
DDR0_CK0_n
DDR0_CKE0
DDR0_CKE1
DDR0_CS0_n
DDR0_CS1_n
DDR0_DM0
DDR0_DM1
DDR0_DM2
DDR0_DM3
DDR0_DQ0
DDR0_DQ1
DDR0_DQ2
DDR0_DQ3
DDR0_DQ4
DDR0_DQ5
DDR0_DQ6
DDR0_DQ7
DDR0_DQ8
DDR0_DQ9
DDR0_DQ10
DDR0_DQ11
DDR0_DQ12
DDR0_DQ13
DDR0_DQ14
DDR0_DQ15
DDR0_DQ16
DDR0_DQ17
DDR0_DQ18
DDR0_DQ19
DDR0_DQ20
DDR0_DQ21
DDR0_DQ22
DDR0_DQ23
DDR0_DQ24
DDR0_DQ25
DDR0_DQ26
DDR0_DQ27
DDR0_DQ28
DDR0_DQ29
DDR0_DQ30
DDR0_DQ31
DDR0_DQS0
DDR0_DQS0_n
DDR0_DQS1
DDR0_DQS1_n
DDR0_DQS2
DDR0_DQS2_n
DDR0_DQS2
DDR0_DQS2_n
DDR0_ODT0
DDR0_ODT1
DDR0_RESET0_n		 If DDRSS is not used, leave unconnected.Note: The DDR0 pins in this list can only be left unconnected when VDDS_DDR and VDDS_DDR_C are connected to VSS. The DDR0 pins must be connected as defined in the DDR Board Design and Layout Guidelines, when VDDS_DDR and VDDS_DDR_C are connected to a power source.
1K3
1J1		 VDD_MMC0
VDDA_0P85_DLL_MMC0		 If MMC0 is not used, each of these balls must be connected to the same power source as VDD_CORE.
1K2 VDDS_MMC0 If MMC0 is not used, each of these balls must be connected to any 1.8-V power source that does not violate device power supply sequencing requirements.
AC5
AA6
AB8
AD5
AC7
AB7
AD6
AE5
AE6
AC6
AA7
AB6		 MMC0_CALPAD
MMC0_CLK
MMC0_CMD
MMC0_DS
MMC0_DAT0
MMC0_DAT1
MMC0_DAT2
MMC0_DAT3
MMC0_DAT4
MMC0_DAT5
MMC0_DAT6
MMC0_DAT7		 If MMC0 is not used, each of these balls must be left unconnected.
1J4
1K5
Y11		 VDDA_CORE_USB
VDDA_1P8_USB
VDDA_3P3_USB		 USB0 and USB1 share these power rails, so each of these balls must be connected to valid power sources when either USB0 or USB1 is used.If USB0 and USB1 are not used, each of these balls must be connected directly to VSS.
AE8
AE7
Y8
Y7
AE10
AE9
1K4
Y10		 USB0_DM
USB0_DP
USB0_RCALIB
USB0_VBUS
USB1_DM
USB1_DP
USB1_RCALIB
USB1_VBUS		 If USB0 or USB1 is not used, leave the respective DM, DP, and VBUS balls unconnected.Note: The USB0_RCALIB and USB1_RCALIB pins can only be left unconnected when VDDA_CORE_USB, VDDA_1P8_USB, and VDDA_3P3_USB are connected to VSS. The USB0_RCALIB and USB1_RCALIB pins must be connected to VSS through separate appropriate external resistors when VDDA_CORE_USB, VDDA_1P8_USB, and VDDA_3P3_USB are connected to power sources.
1K6
IK8
IK7		 VDDA_CORE_CSI_DSI
VDDA_CORE_DSI_CLK
VDDA_1P8_CSI_DSI		 If CSIRX0 and DSITX0 are not used and the device boundary scan function is required, each of these balls must be connected to valid power sources.If CSIRX0 and DSITX0 are not used and the device boundary scan function is not required, each of these balls can alternatively be connected directly to VSS.
AE12
AE11
AB11
AB10
AC10
AC9
AA10
AA9
AD9
AD8
AA15		 CSI0_RXCLKN
CSI0_RXCLKP
CSI0_RXN0
CSI0_RXP0
CSI0_RXN1
CSI0_RXP1
CSI0_RXN2
CSI0_RXP2
CSI0_RXN3
CSI0_RXP3
CSI0_RXRCALIB		 If CSIRX0 is not used, leave unconnected.
AA12
AA13
AD11
AD12
AB13
AB14
AC12
AC13
AE14
AE15
Y16		 DSI0_TXCLKN
DSI0_TXCLKP
DSI0_TXN0
DSI0_TXP0
DSI0_TXN1
DSI0_TXP1
DSI0_TXN2
DSI0_TXP2
DSI0_TXN3
DSI0_TXP3
DSI0_TXRCALIB		 If DSITX0 is not used, leave unconnected.
AE20
AD20
AC19
AD19
AA19
AB19
AD18
AE19
AD17
AD16
AB17
AC17
AC16
AC15
AB16
AA16
AE18
AE17
AD15
AD14		 OLDI0_A0N
OLDI0_A0P
OLDI0_A1N
OLDI0_A1P
OLDI0_A2N
OLDI0_A2P
OLDI0_A3N
OLDI0_A3P
OLDI0_A4N
OLDI0_A4P
OLDI0_A5N
OLDI0_A5P
OLDI0_A6N
OLDI0_A6P
OLDI0_A7N
OLDI0_A7P
OLDI0_CLK0N
OLDI0_CLK0P
OLDI0_CLK1N
OLDI0_CLK1P		 If OLDI0 is not used, leave unconnected.
1A6 VMON_VSYS If VMON_VSYS is not used, this ball must be connected directly to VSS.
1A10
1A4		 VMON_1P8_SOC
VMON_3P3_SOC		 If VMON_1P8_SOC and VMON_3P3_SOC are not used to monitor the SOC power rails, these balls must remain connected to their respective 1.8-V and 3.3-V power rails or connected directly to VSS.
(1) To determine which power supply is associated with any IO, see the POWER column of the Pin Attributes table.

Note:

Internal pull resistors are weak and may not source enough current to maintain a valid logic level for some operating conditions. This can be the case when connected to components with leakage to the opposite logic level, or when external noise sources couple to signal traces attached to balls which are only pulled to a valid logic level by the internal resistor. Therefore, external pull resistors are recommended to hold a valid logic level on balls with external connections.

Many of the device IOs are turned off by default and external pull resistors may be required to hold inputs of any attached device in a valid logic state until software initializes the respective IOs. The state of configurable device IOs are defined in the BALL STATE DURING RESET RX/TX/PULL and BALL STATE AFTER RESET RX/TX/PULL columns of the Pin Attributes table. Any IO with its input buffer (RX) turned off is allowed to float without damaging the device. However, any IO with its input buffer (RX) turned on shall never be allowed to float to any potential between VILSS and VIHSS. The input buffer can enter a high-current state which could damage the IO cell if allowed to float between these levels.