SPRSPA3A March 2024 – September 2024 AM67 , AM67A
PRODUCTION DATA
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Table 6-111 and Figure 6-83 present switching characteristics for MMC1/MMC2 – UHS-I SDR104 Mode.
NO. | PARAMETER | MIN | MAX | UNIT | |
---|---|---|---|---|---|
fop(clk) | Operating frequency, MMCx_CLK | 200 | MHz | ||
SDR1045 | tc(clk) | Cycle time, MMCx_CLK | 5 | ns | |
SDR1046 | tw(clkH) | Pulse duration, MMCx_CLK high | 2.12 | ns | |
SDR1047 | tw(clkL) | Pulse duration, MMCx_CLK low | 2.12 | ns | |
SDR1048 | td(clkL-cmdV) | Delay time, MMCx_CLK rising edge to MMCx_CMD transition | 1.07 | 3.21 | ns |
SDR1049 | td(clkL-dV) | Delay time, MMCx_CLK rising edge to MMCx_DAT[3:0] transition | 1.07 | 3.21 | ns |