JAJSR83 September   2023 AMC131M02

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Insulation Specifications
    6. 6.6  Safety-Related Certifications
    7. 6.7  Safety Limiting Values
    8. 6.8  Electrical Characteristics
    9. 6.9  Timing Requirements
    10. 6.10 Switching Characteristics
    11. 6.11 Timing Diagrams
    12. 6.12 Typical Characteristics
  8. 7 Parameter Measurement Information
    1. 7.1 Noise Measurements
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Isolated DC/DC Converter
        1. 8.3.1.1 DC/DC Converter Failure Detection
      2. 8.3.2  High-Side Current Drive Capability
      3. 8.3.3  Isolation Channel Signal Transmission
      4. 8.3.4  Input ESD Protection Circuitry
      5. 8.3.5  Input Multiplexer
      6. 8.3.6  Programmable Gain Amplifier (PGA)
      7. 8.3.7  Voltage Reference
      8. 8.3.8  Internal Test Signals
      9. 8.3.9  Clocking and Power Modes
      10. 8.3.10 ΔΣ Modulator
      11. 8.3.11 Digital Filter
        1. 8.3.11.1 Digital Filter Implementation
          1. 8.3.11.1.1 Fast-Settling Filter
          2. 8.3.11.1.2 SINC3 and SINC3 + SINC1 Filter
        2. 8.3.11.2 Digital Filter Characteristic
      12. 8.3.12 Channel Phase Calibration
      13. 8.3.13 Calibration Registers
      14. 8.3.14 Register Map CRC
      15. 8.3.15 General-Purpose Digital Output (GPO)
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power-Up and Reset
        1. 8.4.1.1 Power-On Reset
        2. 8.4.1.2 SYNC/RESET Pin
        3. 8.4.1.3 RESET Command
      2. 8.4.2 Start-Up Behavior After Power-Up
      3. 8.4.3 Start-Up Behavior After a Pin Reset or RESET Command
      4. 8.4.4 Start-Up Behavior After a Pause in CLKIN
      5. 8.4.5 Synchronization
      6. 8.4.6 Conversion Modes
        1. 8.4.6.1 Continuous-Conversion Mode
        2. 8.4.6.2 Global-Chop Mode
      7. 8.4.7 Power Modes
      8. 8.4.8 Standby Mode
    5. 8.5 Programming
      1. 8.5.1 Serial Interface
        1. 8.5.1.1  Chip Select (CS)
        2. 8.5.1.2  Serial Data Clock (SCLK)
        3. 8.5.1.3  Serial Data Input (DIN)
        4. 8.5.1.4  Serial Data Output (DOUT)
        5. 8.5.1.5  Data Ready (DRDY)
        6. 8.5.1.6  Conversion Synchronization or System Reset (SYNC/RESET)
        7. 8.5.1.7  SPI Communication Frames
        8. 8.5.1.8  SPI Communication Words
        9. 8.5.1.9  Short SPI Frames
        10. 8.5.1.10 Communication Cyclic Redundancy Check (CRC)
        11. 8.5.1.11 SPI Timeout
      2. 8.5.2 ADC Conversion Data
      3. 8.5.3 Commands
        1. 8.5.3.1 NULL (0000 0000 0000 0000)
        2. 8.5.3.2 RESET (0000 0000 0001 0001)
        3. 8.5.3.3 STANDBY (0000 0000 0010 0010)
        4. 8.5.3.4 WAKEUP (0000 0000 0011 0011)
        5. 8.5.3.5 LOCK (0000 0101 0101 0101)
        6. 8.5.3.6 UNLOCK (0000 0110 0101 0101)
        7. 8.5.3.7 RREG (101a aaaa annn nnnn)
          1. 8.5.3.7.1 Reading a Single Register
          2. 8.5.3.7.2 Reading Multiple Registers
        8. 8.5.3.8 WREG (011a aaaa annn nnnn)
      4. 8.5.4 ADC Output Buffer and FIFO Buffer
      5. 8.5.5 Collecting Data for the First Time or After a Pause in Data Collection
    6. 8.6 AMC131M02 Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Unused Inputs and Outputs
      2. 9.1.2 Antialiasing
      3. 9.1.3 Minimum Interface Connections
      4. 9.1.4 Multiple Device Configuration
      5. 9.1.5 Calibration
      6. 9.1.6 Troubleshooting
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Voltage Measurement
        2. 9.2.2.2 Current Shunt Measurement
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 ドキュメントの更新通知を受け取る方法
    3. 10.3 サポート・リソース
    4. 10.4 Trademarks
    5. 10.5 静電気放電に関する注意事項
    6. 10.6 用語集
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.6 AMC131M02 Registers

Table 8-13 lists the memory-mapped registers for the AMC131M02 registers. All register offset addresses not listed in Table 8-13 should be considered as reserved locations and the register contents should not be modified.

Table 8-13 Register Map
AddressAcronymResetBit 15Bit 14Bit 13Bit 12Bit 11Bit 10Bit 9Bit 8
Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0
00hIDXbRESERVEDCHANCNT[3:0]
RESERVED
01hSTATUS0540hLOCKF_RESYNCREG_MAPCRC_ERRCRC_TYPERESETWLENGTH[1:0]
FUSE_FAILSEC_FAILRESERVEDDRDY1DRDY0
02hMODE0510hRESERVEDREG_CRC_ENRX_CRC_ENCRC_TYPERESETWLENGTH[1:0]
RESERVEDTIMEOUTDRDY_SEL[1:0]DRDY_HiZDRDY_FMT
03hCLOCK030EhRESERVEDCH1_ENCH0_EN
CLK_DIV[1:0]TURBOOSR[2:0]PWR[1:0]
04hGAIN0000hRESERVED
RESERVEDPGAGAIN1[2:0]RESERVEDPGAGAIN0[2:0]
06hCFG0600hRESERVEDGPO_ENGPO_DATGC_DLY[3:0]GC_EN
RESERVED
09hCH0_CFG0000hPHASE0[9:0]
PHASE0[9:0]RESERVEDMUX0[1:0]
0AhCH0_OCAL_MSB0000hOCAL0_MSB[15:0]
OCAL0_MSB[15:0]
0BhCH0_OCAL_LSB0000hOCAL0_LSB[7:0]
RESERVED
0ChCH0_GCAL_MSB8000hGCAL0_MSB[15:0]
GCAL0_MSB[15:0]
0DhCH0_GCAL_LSB0000hGCAL0_LSB[7:0]
RESERVED
0EhCH1_CFG0000hPHASE1[9:0]
PHASE1[9:0]RESERVEDMUX1[1:0]
0FhCH1_OCAL_MSB0000hOCAL1_MSB[15:0]
OCAL1_MSB[15:0]
10hCH1_OCAL_LSB0000hOCAL1_LSB[7:0]
RESERVED
11hCH1_GCAL_MSB8000hGCAL1_MSB[15:0]
GCAL1_MSB[15:0]
12hCH1_GCAL_LSB0000hGCAL1_LSB[7:0]
RESERVED
31hDCDC_CTRL0000hRESERVEDDCDC_FREQ[3:0]
RESERVEDDCDC_EN
3EhREGMAP_CRC0000hREG_CRC[15:0]
REG_CRC[15:0]

Complex bit access types are encoded to fit into small table cells. Table 8-14 shows the codes that are used for access types in this section.

Table 8-14 AMC131M02 Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Write Type
WWWrite
Reset or Default Value
-nValue after reset or the default value

8.6.1 ID Register (Address = 00h) [Reset = 22XXh]

Return to the Summary Table.

Figure 8-31 ID Register
15141312111098
RESERVEDCHANCNT[3:0]
R-0010bR-0010b
76543210
RESERVED
R-X
Table 8-15 ID Register Field Descriptions
BitFieldTypeResetDescription
15:12RESERVEDR0010bReserved
Always reads 0010b
11:8CHANCNT[3:0]R0010bChannel count
Always reads 0010b
7:0RESERVEDRXReserved
Values are subject to change without notice.

8.6.2 STATUS Register (Address = 01h) [Reset = 0540h]

Return to the Summary Table.

Figure 8-32 STATUS Register
15141312111098
LOCKF_RESYNCREG_MAPCRC_ERRCRC_TYPERESETWLENGTH[1:0]
R-0bR-0bR-0bR-0bR-0bR-1bR-01b
76543210
FUSE_FAILSEC_FAILRESERVEDDRDY1DRDY0
R-0bR-1bR-0000bR-0bR-0b
Table 8-16 STATUS Register Field Descriptions
BitFieldTypeResetDescription
15LOCKR0bSPI interface lock indicator
Indicates the SPI interface is locked by the lock command. The bit is reset to 0b by the unlock command.
0b = Unlocked
1b = Locked
14F_RESYNCR0bADC resynchronization indicator
This bit is set each time the ADC resynchronizes. This bit is cleared by reading the STATUS register, either by executing the NULL command or a RREG command accessing the STATUS register.
0b = No resynchronization occurred
1b = Resynchronization occurred
13REG_MAPR0bRegister map CRC fault indicator
Indicates a register map CRC fault occurred. This bit is cleared by reading the STATUS register, either by executing the NULL command or a RREG command accessing the STATUS register.
0b = No register map CRC fault occurred
1b = Register map CRC fault occurred
12CRC_ERRR0bSPI input CRC error indicator
Indicates a SPI input CRC fault occurred. This bit is cleared by reading the STATUS register, either by executing the NULL command or a RREG command accessing the STATUS register.
0b = No CRC error
1b = Input CRC error occurred
11CRC_TYPER0bCRC type indicator
Indicates the CRC type. This bit is cleared by a device reset.
0b = 16-bit CCITT
1b = 16-bit ANSI
10RESETR1bReset status indicator
The device reset indicator is triggered by the RESET pin, power-on-reset or the RESET command. This bit is cleared by writing 0b to the RESET bit in the MODE register.
0b = Not reset
1b = Reset occurred
9:8WLENGTH[1:0]R01bData word length indicator
Indicates the data word frame length. This bit is cleared by a device reset.
00b = 16 bit
01b = 24 bits
10b = 32 bits; zero padding
11b = 32 bits; MSB sign extension
7FUSE_FAILR0bFuse parity fault indicator
Indicates a fault of the internal memory. This bit is cleared by reading the STATUS register, either by executing the NULL command or a RREG command accessing the STATUS register. If the physical fault persists, the indicator is set again automatically.
0b = Fuse parity OK
1b = Fuse parity not OK
6SEC_FAILR1bHigh-side supply fault indicator
Indicates a fault of the high-side output of the DC/DC converter, or a communication error during the data transmission across the isolation barrier. This bit is cleared by reading the STATUS register, either by executing the NULL command or a RREG command accessing the STATUS register.
0b = High-side supply OK
1b = High-side supply not OK
5:2RESERVEDR0000bReserved
Always reads 0000b
1DRDY1R0bChannel 1 ADC data available indicator

0b = No new data available
1b = New data are available
0DRDY0R0bChannel 0 ADC data available indicator

0b = No new data available
1b = New data are available

8.6.3 MODE Register (Address = 02h) [Reset = 0510h]

Return to the Summary Table.

Figure 8-33 MODE Register
15141312111098
RESERVEDREG_CRC_ENRX_CRC_ENCRC_TYPERESETWLENGTH[1:0]
R/W-00bR/W-0bR/W-0bR/W-0bR/W-1bR/W-01b
76543210
RESERVEDTIMEOUTDRDY_SEL[1:0]DRDY_HiZDRDY_FMT
R/W-000bR/W-1bR/W-00bR/W-0bR/W-0b
Table 8-17 MODE Register Field Descriptions
BitFieldTypeResetDescription
15:14RESERVEDR/W00bReserved
Always write 00b
13REG_CRC_ENR/W0bRegister map CRC enable

0b = Disabled
1b = Enabled
12RX_CRC_ENR/W0bSPI input CRC enable

0b = Disabled
1b = Enabled
11CRC_TYPER/W0bSPI input and output, register map CRC type

0b = 16-bit CCITT
1b = 16-bit ANSI
10RESETR/W1bReset
Write 0b to clear the RESET bit in the STATUS register
0b = No reset
1b = Reset occurred
9:8WLENGTH[1:0]R/W01bData word length selection

00b = 16 bits
01b = 24 bits
10b = 32 bits; LSB zero padding
11b = 32 bits; MSB sign extension
7:5RESERVEDR/W000bReserved
Always write 000b
4TIMEOUTR/W1bSPI timeout enable

0b = Disabled
1b = Enabled
3:2DRDY_SEL[1:0]R/W00bDRDY pin signal source selection

00b = Most lagging enabled channel
01b = Logic OR of all the enabled channels
10b = Most leading enabled channel
11b = Most leading enabled channel
1DRDY_HiZR/W0bDRDY pin state when conversion data are not available

0b = Logic high
1b = High impedance
0DRDY_FMTR/W0bDRDY signal format when conversion data are available

0b = Logic low
1b = Low pulse with a fixed duration

8.6.4 CLOCK Register (Address = 03h) [Reset = 030Eh]

Return to the Summary Table.

Figure 8-34 CLOCK Register
15141312111098
RESERVEDCH1_ENCH0_EN
R/W-000000bR/W-1bR/W-1b
76543210
CLK_DIV[1:0]TURBOOSR[2:0]PWR[1:0]
R/W-00bR/W-0bR/W-011bR/W-10b
Table 8-18 CLOCK Register Field Descriptions
BitFieldTypeResetDescription
15:10RESERVEDR/W000000bReserved
Always write 000000b
9CH1_ENR/W1bChannel 1 ADC enable

0b = Disabled
1b = Enabled
8CH0_ENR/W1bChannel 0 ADC enable

0b = Disabled
1b = Enabled
7:6CLK_DIV[1:0]R/W00bClock divider ratio selection

00b = Divide by 2
01b = Divide by 4
10b = Divide by 8
11b = Divide by 12
5TURBOR/W0bTurbo mode (OSR = 64)
Selects oversampling ratio 64 by setting this bit to 1b. The OSR[2:0] bits are ignored if this bit is set to 1b.
0b = Disabled
1b = Enabled
4:2OSR[2:0]R/W011bModulator oversampling ratio selection

000b = 128
001b = 256
010b = 512
011b = 1024
100b = 2048
101b = 4096
110b = 8192
111b = 16384
1:0PWR[1:0]R/W10bPower mode selection

00b = Reserved. Do not use.
01b = Low power
10b = High resolution
11b = Reserved. Do not use.

8.6.5 GAIN Register (Address = 04h) [Reset = 0000h]

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Figure 8-35 GAIN Register
15141312111098
RESERVED
R/W-00000000b
76543210
RESERVEDPGAGAIN1[2:0]RESERVEDPGAGAIN0[2:0]
R/W-0bR/W-000bR/W-0bR/W-000b
Table 8-19 GAIN Register Field Descriptions
BitFieldTypeResetDescription
15:8RESERVEDR/W00000000b
Always write 00000000b
7RESERVEDR/W0b
Always write 0b
6:4PGAGAIN1[2:0]R/W000bPGA gain selection for channel 1

000b = 1
001b = 2
010b = 4
011b = 8
100b = 16
101b = 32
110b = 64
111b = 128
3RESERVEDR/W0bReserved
Always write 0b
2:0PGAGAIN0[2:0]R/W000bPGA gain selection for channel 0

000b = 1
001b = 2
010b = 4
011b = 8
100b = 16
101b = 32
110b = 64
111b = 128

8.6.6 CFG Register (Address = 06h) [Reset = 0600h]

Return to the Summary Table.

Figure 8-36 CFG Register
15141312111098
RESERVEDGPO_ENGPO_DATGC_DLY[3:0]GC_EN
R/W-0bR/W-0bR/W-0bR/W-0011bR/W-0b
76543210
RESERVED
R/W-00000000b
Table 8-20 CFG Register Field Descriptions
BitFieldTypeResetDescription
15RESERVEDR/W0bReserved
Always write 0b
14GPO_ENR/W0bDigital output enable
Enables digital output (GPO) functionality at AIN2P pin.
0b = Digital output disabled
1b = Digital output enabled
13GPO_DATR/W0bDigital output data
Digital output (GPO) data if GPO_EN = 1b.
0b = Zero output
1b = One output
12:9GC_DLY[3:0]R/W0011bGlobal-chop delay selection
Delay in modulator clock periods before measurement begins.
0000b = 2
0001b = 4
0010b = 8
0011b = 16
0100b = 32
0101b = 64
0110b = 128
0111b = 256
1000b = 512
1001b = 1024
1010b = 2048
1011b = 4096
1100b = 8192
1101b = 16384
1110b = 32768
1111b = 65536
8GC_ENR/W0bGlobal-chop enable

0b = Disabled
1b = Enabled
7:0RESERVEDR/W00000000bReserved
Always write 00000000b

8.6.7 CH0_CFG Register (Address = 09h) [Reset = 0000h]

Return to the Summary Table.

Figure 8-37 CH0_CFG Register
15141312111098
PHASE0[9:0]
R/W-0000000000b
76543210
PHASE0[9:0]RESERVEDMUX0[1:0]
R/W-0000000000bR-0000bR/W-00b
Table 8-21 CH0_CFG Register Field Descriptions
BitFieldTypeResetDescription
15:6PHASE0[9:0]R/W0000000000bChannel 0 phase delay selection
Phase delay in modulator clock cycles provided in twos complement format.
5:2RESERVEDR0000bReserved
Always reads 0000b
1:0MUX0[1:0]R/W00bChannel 0 input selection
Input multiplexer for channel 0
00b = AIN0P and AIN0N
01b = AIN0 disconnected (ADC inputs shorted)
10b = DC diagnostic signal
11b = AC diagnostic signal

8.6.8 CH0_OCAL_MSB Register (Address = 0Ah) [Reset = 0000h]

Return to the Summary Table.

Figure 8-38 CH0_OCAL_MSB Register
15141312111098
OCAL0_MSB[15:0]
R/W-0000000000000000b
76543210
OCAL0_MSB[15:0]
R/W-0000000000000000b
Table 8-22 CH0_OCAL_MSB Register Field Descriptions
BitFieldTypeResetDescription
15:0OCAL0_MSB[15:0]R/W0000000000000000bChannel 0 offset calibration register bits [23:8]
Value provided in twos complement format.

8.6.9 CH0_OCAL_LSB Register (Address = 0Bh) [Reset = 0000h]

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Figure 8-39 CH0_OCAL_LSB Register
15141312111098
OCAL0_LSB[7:0]
R/W-00000000b
76543210
RESERVED
R-00000000b
Table 8-23 CH0_OCAL_LSB Register Field Descriptions
BitFieldTypeResetDescription
15:8OCAL0_LSB[7:0]R/W00000000bChannel 0 offset calibration register bits [7:0]
Value provided in twos complement format.
7:0RESERVEDR00000000bReserved
Always reads 00000000b

8.6.10 CH0_GCAL_MSB Register (Address = 0Ch) [Reset = 8000h]

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Figure 8-40 CH0_GCAL_MSB Register
15141312111098
GCAL0_MSB[15:0]
R/W-1000000000000000b
76543210
GCAL0_MSB[15:0]
R/W-1000000000000000b
Table 8-24 CH0_GCAL_MSB Register Field Descriptions
BitFieldTypeResetDescription
15:0GCAL0_MSB[15:0]R/W1000000000000000bChannel 0 gain calibration register bits [23:8]
Unsigned number for the gain range from 0.0 to 2.0 x (224 – 1) / 224

8.6.11 CH0_GCAL_LSB Register (Address = 0Dh) [Reset = 0000h]

Return to the Summary Table.

Figure 8-41 CH0_GCAL_LSB Register
15141312111098
GCAL0_LSB[7:0]
R/W-00000000b
76543210
RESERVED
R-00000000b
Table 8-25 CH0_GCAL_LSB Register Field Descriptions
BitFieldTypeResetDescription
15:8GCAL0_LSB[7:0]R/W00000000bChannel 0 gain calibration register bits [7:0]
Unsigned number for the gain range from 0.0 to 2.0 x (224 – 1) / 224
7:0RESERVEDR00000000bReserved
Always reads 00000000b

8.6.12 CH1_CFG Register (Address = 0Eh) [Reset = 0000h]

Return to the Summary Table.

Figure 8-42 CH1_CFG Register
15141312111098
PHASE1[9:0]
R/W-0000000000b
76543210
PHASE1[9:0]RESERVEDMUX1[1:0]
R/W-0000000000bR-0000bR/W-00b
Table 8-26 CH1_CFG Register Field Descriptions
BitFieldTypeResetDescription
15:6PHASE1[9:0]R/W0000000000bChannel 1 phase delay selection
Phase delay in modulator clock cycles provided in twos complement format.
5:2RESERVEDR0000bReserved
Always reads 0000b
1:0MUX1[1:0]R/W00bChannel 1 input selection
Input multiplexer for channel 1
00b = AIN1P and AIN1N
01b = AIN1 disconnected (ADC inputs shorted)
10b = DC diagnostic signal
11b = AC diagnostic signal

8.6.13 CH1_OCAL_MSB Register (Address = 0Fh) [Reset = 0000h]

Return to the Summary Table.

Figure 8-43 CH1_OCAL_MSB Register
15141312111098
OCAL1_MSB[15:0]
R/W-0000000000000000b
76543210
OCAL1_MSB[15:0]
R/W-0000000000000000b
Table 8-27 CH1_OCAL_MSB Register Field Descriptions
BitFieldTypeResetDescription
15:0OCAL1_MSB[15:0]R/W0000000000000000bChannel 1 offset calibration register bits [23:8]
Value provided in twos complement format.

8.6.14 CH1_OCAL_LSB Register (Address = 10h) [Reset = 0000h]

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Figure 8-44 CH1_OCAL_LSB Register
15141312111098
OCAL1_LSB[7:0]
R/W-00000000b
76543210
RESERVED
R-00000000b
Table 8-28 CH1_OCAL_LSB Register Field Descriptions
BitFieldTypeResetDescription
15:8OCAL1_LSB[7:0]R/W00000000bChannel 1 offset calibration register bits [7:0]
Value provided in twos complement format.
7:0RESERVEDR00000000bReserved
Always reads 00000000b

8.6.15 CH1_GCAL_MSB Register (Address = 11h) [Reset = 8000h]

Return to the Summary Table.

Figure 8-45 CH1_GCAL_MSB Register
15141312111098
GCAL1_MSB[15:0]
R/W-1000000000000000b
76543210
GCAL1_MSB[15:0]
R/W-1000000000000000b
Table 8-29 CH1_GCAL_MSB Register Field Descriptions
BitFieldTypeResetDescription
15:0GCAL1_MSB[15:0]R/W1000000000000000bChannel 1 gain calibration register bits [23:8]
Unsigned number for the gain range from 0.0 to 2.0 x (224 – 1) / 224

8.6.16 CH1_GCAL_LSB Register (Address = 12h) [Reset = 0000h]

Return to the Summary Table.

Figure 8-46 CH1_GCAL_LSB Register
15141312111098
GCAL1_LSB[7:0]
R/W-00000000b
76543210
RESERVED
R-00000000b
Table 8-30 CH1_GCAL_LSB Register Field Descriptions
BitFieldTypeResetDescription
15:8GCAL1_LSB[7:0]R/W00000000bChannel 1 gain calibration register bits [7:0]
Unsigned number for the gain range from 0.0 to 2.0 x (224 – 1) / 224
7:0RESERVEDR00000000bReserved
Always reads 00000000b

8.6.17 DCDC_CTRL Register (Address = 31h) [Reset = 0000h]

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Figure 8-47 DCDC_CTRL Register
15141312111098
RESERVEDDCDC_FREQ[3:0]
R/W-0000bR/W-0000b
76543210
RESERVEDDCDC_EN
R/W-0000000bR/W-0b
Table 8-31 DCDC_CTRL Register Field Descriptions
BitFieldTypeResetDescription
15:12RESERVEDR/W0000bReserved
Always write 0000b
11:8DCDC_FREQ[3:0]R/W0000bDC/DC frequency range selection
Selects the range of the modulator clock frequency, based on the frequency at the CLKIN pin and clock divider ratio.
0000b = 3.76 MHz to 4.10 MHz
0001b = 3.52 MHz to 3.84 MHz
0010b = 3.30 MHz to 3.59 MHz
0011b = 3.09 MHz to 3.36 MHz
0100b = 2.89 MHz to 3.15 MHz
0101b = 2.71 MHz to 2.95 MHz
0110b = 2.53 MHz to 2.76 MHz
0111b = 2.37 MHz to 2.59 MHz
1000b = 2.22 MHz to 2.42 MHz
1001b = 2.08 MHz to 2.27 MHz
1010b = 1.95 MHz to 2.12 MHz
1011b = 1.82 MHz to 1.99 MHz
1100b = 1.71 MHz to 1.86 MHz
1101b = 1.60 MHz to 1.74 MHz
1110b = 1.50 MHz to 1.63 MHz
1111b = 1.40 MHz to 1.53 MHz
7:1RESERVEDR/W0000000bReserved
Always write 0000000b
0DCDC_ENR/W0bDC/DC enable
Enables the integrated DC/DC converter.
0b = Disabled
1b = Enabled

8.6.18 REGMAP_CRC Register (Address = 3Eh) [Reset = 0000h]

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Figure 8-48 REGMAP_CRC Register
15141312111098
REG_CRC[15:0]
R-0000000000000000b
76543210
REG_CRC[15:0]
R-0000000000000000b
Table 8-32 REGMAP_CRC Register Field Descriptions
BitFieldTypeResetDescription
15:0REG_CRC[15:0]R0000000000000000bRegister map CRC value