JAJSEW2D May   2017  – December 2021 AWR1243

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Functional Block Diagram
  5. 5 Revision History
  6. 6 Device Comparison
    1. 6.1 Related Products
  7. 7 Terminal Configuration and Functions
    1. 7.1 Pin Diagram
    2. 7.2 Signal Descriptions
      1. 7.2.1 Signal Descriptions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Power-On Hours (POH)
    4. 8.4 Recommended Operating Conditions
    5. 8.5 Power Supply Specifications
    6. 8.6 Power Consumption Summary
    7. 8.7 RF Specification
    8. 8.8 Thermal Resistance Characteristics for FCBGA Package [ABL0161]
    9. 8.9 Timing and Switching Characteristics
      1. 8.9.1 Power Supply Sequencing and Reset Timing
      2. 8.9.2 Synchronized Frame Triggering
      3. 8.9.3 Input Clocks and Oscillators
        1. 8.9.3.1 Clock Specifications
      4. 8.9.4 Multibuffered / Standard Serial Peripheral Interface (MibSPI)
        1. 8.9.4.1 Peripheral Description
          1. 8.9.4.1.1 SPI Timing Conditions
          2. 8.9.4.1.2 SPI Peripheral Mode Switching Parameters (SPICLK = input, SPISIMO = input, and SPISOMI = output)
          3. 8.9.4.1.3 SPI Peripheral Mode Timing Requirements (SPICLK = input, SPISIMO = input, and SPISOMI = output)
        2. 8.9.4.2 Typical Interface Protocol Diagram (Peripheral Mode)
      5. 8.9.5 LVDS Interface Configuration
        1. 8.9.5.1 LVDS Interface Timings
      6. 8.9.6 General-Purpose Input/Output
        1. 8.9.6.1 Switching Characteristics for Output Timing versus Load Capacitance (CL)
      7. 8.9.7 Camera Serial Interface (CSI)
        1. 8.9.7.1 CSI Switching Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Subsystems
      1. 9.3.1 RF and Analog Subsystem
        1. 9.3.1.1 Clock Subsystem
        2. 9.3.1.2 Transmit Subsystem
        3. 9.3.1.3 Receive Subsystem
      2. 9.3.2 Host Interface
    4. 9.4 Other Subsystems
      1. 9.4.1 ADC Data Format Over CSI2 Interface
  10. 10Monitoring and Diagnostics
    1. 10.1 Monitoring and Diagnostic Mechanisms
  11. 11Applications, Implementation, and Layout
    1. 11.1 Application Information
    2. 11.2 Short-, Medium-, and Long-Range Radar
    3. 11.3 Reference Schematic
  12. 12Device and Documentation Support
    1. 12.1 Device Nomenclature
    2. 12.2 Tools and Software
    3. 12.3 Documentation Support
    4. 12.4 サポート・リソース
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Packaging Information
    2. 13.2 Tray Information for

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • ABL|161
サーマルパッド・メカニカル・データ
発注情報

8.4 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VDDIN 1.2 V digital power supply 1.14 1.2 1.32 V
VIN_SRAM 1.2 V power rail for internal SRAM 1.14 1.2 1.32 V
VNWA 1.2 V power rail for SRAM array back bias 1.14 1.2 1.32 V
VIOIN I/O supply (3.3 V or 1.8 V):
All CMOS I/Os would operate on this supply.		 3.135 3.3 3.465 V
1.71 1.8 1.89
VIOIN_18 1.8 V supply for CMOS IO 1.71 1.8 1.9 V
VIN_18CLK 1.8 V supply for clock module 1.71 1.8 1.9 V
VIOIN_18DIFF 1.8 V supply for CSI2 port 1.71 1.8 1.9 V
VIN_13RF1 1.3 V Analog and RF supply. VIN_13RF1 and VIN_13RF2 could be shorted on the board 1.23 1.3 1.36 V
VIN_13RF2
VIN_13RF1
(1-V Internal LDO bypass mode)		 0.95 1 1.05 V
VIN_13RF2
(1-V Internal LDO bypass mode)
VIN18BB 1.8-V Analog baseband power supply 1.71 1.8 1.9 V
VIN_18VCO 1.8V RF VCO supply 1.71 1.8 1.9 V
VIH Voltage Input High (1.8 V mode) 1.17 V
Voltage Input High (3.3 V mode) 2.25
VIL Voltage Input Low (1.8 V mode) 0.3*VIOIN V
Voltage Input Low (3.3 V mode) 0.62
VOH High-level output threshold (IOH = 6 mA) VIOIN – 450 mV
VOL Low-level output threshold (IOL = 6 mA) 450 mV
NRESET SOP[2:0] VIL (1.8V Mode) 0.2 V
VIH (1.8V Mode) 0.96
VIL (3.3V Mode) 0.3
VIH (3.3V Mode) 1.57