JAJSC39A December 2011 – October 2014
PRODUCTION DATA.
MIN | MAX | UNIT | ||
---|---|---|---|---|
DC voltage applied to VPU See Figure 1 | –0.3 | 12.5 | V | |
Low-level output current, IOL | 5 | mA | ||
ESD IEC 61000-4-2 Air discharge | SDQ to VSS, VSS to SDQ | 6 | kV | |
Operating free-air temperature range, TA | –20 | 70 | °C |
MIN | MAX | UNIT | |||
---|---|---|---|---|---|
Tstg | Storage temperature range | –55 | 125 | °C |
PARAMETER | TEST CONDITION | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
ISDQ | Supply current | VPU = 5.5 V | 20 | μA | ||
VOL | Low-level output voltage | Logic 0, VPU = 5.5 V, IOL = 4 mA, SDQ pin | 0.4 | V | ||
Logic 0, VPU = 2.65 V, IOL = 2 mA | 0.4 | V | ||||
VOH | High-level output voltage | Logic 1 | VPU | 5.5 | V | |
IOL | Low-level output current (sink) | VOL = 0.4 V, SDQ pin | 4 | mA | ||
VIL | Low-level input voltage | Logic 0 | 0.8 | V | ||
VIH | High-level input voltage | Logic 1 | 2.2 | V | ||
VPP | Programming voltage | 11.5 | 12 | V | ||
Ilkg | Input leakage | 1.4 | µA | |||
CI | Input capacitance | 1.2 | nF |
PARAMETER | TEST CONDITION | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
tc | Bit cycle time (1) | 60 | 120 | μs | ||
tWSTRB | Write start cycle (1) | 1 | 15 | μs | ||
tWDSU | Write data setup (1) | tWSTRB | 15 | μs | ||
tWDH | Write data hold (1) (2) | 60 | tc | μs | ||
trec | Recovery time (1) | 1 | μs | |||
tRSTRB | Read start cycle (1) | 1 | 13 | μs | ||
tODD | Output data delay (1) | tRSTRB | 13 | μs | ||
tODHO | Output data hold (1) | 17 | 60 | μs | ||
tRST | Reset time (1) | 480 | μs | |||
tPPD | Presence pulse delay (1) | 15 | 64 | μs | ||
tPP | Presence pulse (1) | 60 | 240 | μs | ||
tEPROG | EPROM programming time | 480 | μs | |||
tPSU | Program setup time | 5 | μs | |||
tPREC | Program recovery time | 5 | μs | |||
tPRE | Program rising-edge time | 5 | μs | |||
tPFE | Program falling-edge time | 5 | μs | |||
tRSTREC | 480 | μs |