JAJSND8C September   2021  – January 2023 BQ25180

PRODUCTION DATA  

  1. 特長
  2. アプリケーション
  3. 概要
  4. Revision History
  5. 概要 (続き)
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Thermal Information
    4. 7.4 Recommended Operating Conditions
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
      1. 8.1.1 Battery Charging Process
        1. 8.1.1.1 Trickle Charge
        2. 8.1.1.2 Precharge
        3. 8.1.1.3 Fast Charge
        4. 8.1.1.4 Termination
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Input Voltage Based Dynamic Power Management (VINDPM)
      2. 8.3.2  Dynamic Power Path Management Mode (DPPM)
      3. 8.3.3  Battery Supplement Mode
      4. 8.3.4  SYS Power Control (SYS_MODE bit control)
        1. 8.3.4.1 SYS Pulldown Control
      5. 8.3.5  SYS Regulation
      6. 8.3.6  ILIM Control
      7. 8.3.7  Protection Mechanisms
        1. 8.3.7.1 Input Overvoltage Protection
        2. 8.3.7.2 Battery Undervoltage Lockout
        3. 8.3.7.3 System Overvoltage Protection
        4. 8.3.7.4 System Short Protection
        5. 8.3.7.5 Battery Overcurrent Protection
        6. 8.3.7.6 Safety Timer and Watchdog Timer
        7. 8.3.7.7 Thermal Protection and Thermal Regulation
      8. 8.3.8  Pushbutton Wake and Reset Input
        1. 8.3.8.1 Pushbutton Wake or Short Button Press Functions
        2. 8.3.8.2 Pushbutton Reset or Long Button Press Functions
      9. 8.3.9  15-Second Timeout for HW Reset
      10. 8.3.10 Hardware Reset
      11. 8.3.11 Software Reset
      12. 8.3.12 Interrupt Indicator (/INT) Pin
      13. 8.3.13 External NTC Monitoring (TS)
        1. 8.3.13.1 TS Biasing and Function
      14. 8.3.14 I2C Interface
        1. 8.3.14.1 F/S Mode Protocol
    4. 8.4 Device Functional Modes
    5. 8.5 Register Maps
      1. 8.5.1 I2C Registers
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Input (IN/SYS) Capacitors
        2. 9.2.2.2 TS
        3. 9.2.2.3 Recommended Passive Components
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 サード・パーティ製品に関する免責事項
    2. 12.2 ドキュメントの更新通知を受け取る方法
    3. 12.3 サポート・リソース
    4. 12.4 Trademarks
    5. 12.5 静電気放電に関する注意事項
    6. 12.6 用語集
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ(パッケージ|ピン)
  • YBG|8
サーマルパッド・メカニカル・データ
発注情報

F/S Mode Protocol

The master initiates a data transfer by generating a start condition. The start condition is when a high-to-low transition occurs on the SDA line while SCL is high, as shown in #GUID-9D85780B-9781-4A69-945E-7C7CC50240D6. All I2C-compatible devices should recognize a start condition.

GUID-ABEA9806-6A5D-4ADC-BC90-B7259F8DE433-low.gif Figure 8-6 START and STOP Condition

The master then generates the SCL pulses, and transmits the 8-bit address and the read/write direction bit R/W on the SDA line. During all transmissions, the master ensures that data is valid. A valid data condition requires the SDA line to be stable during the entire high period of the clock pulse (see #GUID-E607AF0E-98BE-492E-BA7A-602B15A80972). All devices recognize the address sent by the master and compare it to their internal fixed addresses. Only the slave device with a matching address generates an acknowledge (see #GUID-0F49730F-C3A2-426E-9FE3-D8779BFF3014) by pulling the SDA line low during the entire high period of the ninth SCL cycle. Upon detecting this acknowledge, the master knows that communication link with a slave has been established.

GUID-3D2056D6-B420-4DD7-97BC-C77478387852-low.gif Figure 8-7 Bit Transfer on the Serial Interface

The master generates further SCL cycles to either transmit data to the slave (R/W bit 1) or receive data from the slave (R/W bit 0). In either case, the receiver needs to acknowledge the data sent by the transmitter. So an acknowledge signal can either be generated by the master or by the slave, depending on which one is the receiver. The 9-bit valid data sequences consisting of 8-bit data and 1-bit acknowledge can continue as long as necessary. To signal the end of the data transfer, the master generates a stop condition by pulling the SDA line from low to high while the SCL line is high (see #GUID-9D85780B-9781-4A69-945E-7C7CC50240D6). This releases the bus and stops the communication link with the addressed slave. All I2C compatible devices must recognize the stop condition. Upon the receipt of a stop condition, all devices know that the bus is released, and wait for a start condition followed by a matching address. If a transaction is terminated prematurely, the master needs to send a STOP condition to prevent the slave I2C logic from remaining in an incorrect state. Attempting to read data from register addresses not listed in this section will result in FFh being read out.

GUID-A8D6EF42-D2FD-4F9D-A4AF-4B2F8276A97F-low.gif Figure 8-8 Ackowledge on the I2C Bus
GUID-A83B7E1F-5DBB-4FE8-88AB-00BF3E7215FB-low.gif Figure 8-9 Bus Protocol