JAJSS91 November   2023 BQ25756E

PRODUCTION DATA  

  1.   1
  2. 特長
  3. アプリケーション
  4. 概要
  5. 概要 (続き)
  6. Device Comparison
  7. Pin Configuration and Functions
  8. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics (BQ25756E)
  9. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Device Power-On-Reset
      2. 8.3.2  Device Power-Up From Battery Without Input Source
      3. 8.3.3  Device Power Up from Input Source
        1. 8.3.3.1 VAC Operating Window Programming (ACUV and ACOV)
        2. 8.3.3.2 REGN Regulator (REGN LDO)
        3. 8.3.3.3 Compensation-Free Buck-Boost Converter Operation
          1. 8.3.3.3.1 Light-Load Operation
        4. 8.3.3.4 Switching Frequency and Synchronization (FSW_SYNC)
        5. 8.3.3.5 Device HIZ Mode
      4. 8.3.4  Battery Charging Management
        1. 8.3.4.1 Autonomous Charging Cycle
          1. 8.3.4.1.1 Charge Current Programming (ICHG pin and ICHG_REG)
        2. 8.3.4.2 Li-Ion Battery Charging Profile
        3. 8.3.4.3 LiFePO4 Battery Charging Profile
        4. 8.3.4.4 Charging Termination for Li-ion and LiFePO4
        5. 8.3.4.5 Charging Safety Timer
        6. 8.3.4.6 CV Timer
        7. 8.3.4.7 Thermistor Qualification
          1. 8.3.4.7.1 JEITA Guideline Compliance in Charge Mode
          2. 8.3.4.7.2 Cold/Hot Temperature Window in Reverse Mode
      5. 8.3.5  Power Management
        1. 8.3.5.1 Dynamic Power Management: Input Voltage and Input Current Regulation
          1. 8.3.5.1.1 Input Current Regulation
            1. 8.3.5.1.1.1 ILIM_HIZ Pin
          2. 8.3.5.1.2 Input Voltage Regulation
            1. 8.3.5.1.2.1 Max Power Point Tracking (MPPT) for Solar PV Panel
      6. 8.3.6  Reverse Mode Power Direction
      7. 8.3.7  Integrated 16-Bit ADC for Monitoring
      8. 8.3.8  Status Outputs (PG, STAT1, STAT2, and INT)
        1. 8.3.8.1 Power Good Indicator (PG)
        2. 8.3.8.2 Charging Status Indicator (STAT1, STAT2 Pins)
        3. 8.3.8.3 Interrupt to Host (INT)
      9. 8.3.9  Protections
        1. 8.3.9.1 Voltage and Current Monitoring
          1. 8.3.9.1.1 VAC Over-voltage Protection (VAC_OVP)
          2. 8.3.9.1.2 VAC Under-voltage Protection (VAC_UVP)
          3. 8.3.9.1.3 Battery Over-voltage Protection (BAT_OVP)
          4. 8.3.9.1.4 Battery Over-current Protection (BAT_OCP)
          5. 8.3.9.1.5 Reverse Mode Over-voltage Protection (REV_OVP)
          6. 8.3.9.1.6 Reverse Mode Under-voltage Protection (REV_UVP)
          7. 8.3.9.1.7 DRV_SUP Under-voltage and Over-voltage Protection (DRV_OKZ)
          8. 8.3.9.1.8 REGN Under-voltage Protection (REGN_OKZ)
        2. 8.3.9.2 Thermal Shutdown (TSHUT)
      10. 8.3.10 Serial Interface
        1. 8.3.10.1 Data Validity
        2. 8.3.10.2 START and STOP Conditions
        3. 8.3.10.3 Byte Format
        4. 8.3.10.4 Acknowledge (ACK) and Not Acknowledge (NACK)
        5. 8.3.10.5 Target Address and Data Direction Bit
        6. 8.3.10.6 Single Write and Read
        7. 8.3.10.7 Multi-Write and Multi-Read
    4. 8.4 Device Functional Modes
      1. 8.4.1 Host Mode and Default Mode
      2. 8.4.2 Register Bit Reset
    5. 8.5 BQ25756E Registers
  10. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Typical Application
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 ACUV / ACOV Input Voltage Operating Window Programming
          2. 9.2.1.2.2 Charge Voltage Selection
          3. 9.2.1.2.3 Switching Frequency Selection
          4. 9.2.1.2.4 Inductor Selection
          5. 9.2.1.2.5 Input (VAC) Capacitor
          6. 9.2.1.2.6 Output (VBAT) Capacitor
          7. 9.2.1.2.7 Sense Resistor (RAC_SNS and RBAT_SNS) and Current Programming
          8. 9.2.1.2.8 Power MOSFETs Selection
          9. 9.2.1.2.9 Converter Fast Transient Response
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Typical Application (USB-PD EPR Configuration)
        1. 9.2.2.1 Design Requirements
  11. 10Power Supply Recommendations
  12. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  13. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 サード・パーティ製品に関する免責事項
    2. 12.2 ドキュメントの更新通知を受け取る方法
    3. 12.3 サポート・リソース
    4. 12.4 Trademarks
    5. 12.5 静電気放電に関する注意事項
    6. 12.6 用語集
  14. 13Revision History
  15. 14Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Host Mode and Default Mode

The device is a host controlled charger, but it can operate in default mode without host management. In default mode, the device can be used as an autonomous charger with no host or while host is in sleep mode. When the charger is in default mode, WD_STAT bit becomes HIGH, WD_FLAG is set to 1, and a INT is asserted low to alert the host (unless masked by WD_MASK). The WD_FLAG bit would read as a '1' upon the first read and then '0' upon subsequent reads. When the charger is in host mode, WD_STAT bit is LOW.

After power-on-reset, the device starts in default mode with watchdog timer expired. All the registers are in the default settings.

In default mode, the device keeps charging the battery with default 2-hour pre-charging safety timer and the 12-hour fast charging safety timer. At the end of the 2-hour or 12-hour timer expiration, the charging is stopped if termination has not been detected.

A write to any I2C register transitions the charger from default mode to host mode, and initiates the watchdog timer. All the device parameters can be programmed by the host. To keep the device in host mode, the host has to reset the watchdog timer by writing 1 to WD_RST bit before the watchdog timer expires (WD_STAT bit is set), or disable watchdog timer by setting WATCHDOG bits = 00.

When the watchdog timer is expired, the device returns to default mode and select registers are reset to default values as detailed in the Register Map section. The Watchdog timer will be reset on any write if the watchdog timer has expired. When watchdog timer expires, WD_STAT and WD_FLAG is set to 1, and /INT is asserted low to alert the host (unless masked by WD_MASK).

GUID-1CEF2E4E-9657-457C-962E-49C07BA8C33D-low.gif Figure 8-15 Watchdog Timer Flow Chart