JAJSMA5C June   2021  – March 2022 BUF802

PRODUCTION DATA  

  1. 特長
  2. アプリケーション
  3. 説明
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics: Wide Bandwidth Mode
    6. 6.6 Electrical Characteristics: Low Quiescent Current Mode
    7. 6.7 Typical Characteristics
  7. Parameter Measurement Information
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Input and Output Over-Voltage Clamp
      2. 8.3.2 Adjustable Quiescent Current
      3. 8.3.3 ESD Structure
    4. 8.4 Device Functional Modes
      1. 8.4.1 Buffer Mode (BF Mode)
      2. 8.4.2 Composite Loop Mode (CL Mode)
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Oscilloscope Front-End Amplifier Design
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Transforming a Wide-Bandwidth, 50 Ω Input Signal Chain to High-Input Impedance
        1. 9.2.2.1 Detailed Design Results
        2. 9.2.2.2 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 サポート・リソース
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Composite Loop Mode (CL Mode)

GUID-20210302-CA0I-ZSHS-6NDH-MW7B9CJMDFF8-low.pngFigure 8-12 Internal Schematic – CL Mode
GUID-20210224-CA0I-BBGV-BDZH-1QVVSWCGSXJS-low.gifFigure 8-13 CL Mode Frequency Response

The 330 pF input series capacitor shown in Figure 8-12 splits the input signal into a low-frequency and high-frequency component. These signals are applied to In_Aux and IN respectively. The IN pin controls the output of BUF802 through the Main Path, whereas the In_Aux pin controls the output through the Auxiliary Path.

The transfer function of the composite loop in CL Mode can be split into the following 3 frequency regions:

  1. Low Frequency Region: The gain of the composite loop in the low-frequency region is α/β (determined by α and β network). In the low-frequency region the 330 pF input capacitor presents a high-impedance in the Main Path, causing the signal to flow through the precision amplifier and the In_Aux pin. This region spans from DC to fLF. fLF is the pole resulting from the gain bandwidth of the precision amplifier, the Auxiliary Path bandwidth, and parasitic capacitance of the components along the path.
  2. High Frequency Region: In the high-frequency region, the precision amplifier and the Auxiliary Path run out of bandwidth. The net gain of the composite loop in this region is determined solely by the Main Path gain of the BUF802, which is denoted by G. This region spans from the pole created at fHF till the LSBW of the BUF802. The fHF is the pole resulting from the 330 pF series capacitor and the 10 MΩ resistor on the In_Bias pin.
  3. Cross-over Frequency Region: the Main Path and Auxiliary Path work in conjunction to determine the gain in the crossover region. To maintain a flat frequency response in this region, the following conditions have to be met:
    1. α/β = G
    2. High frequency response pole fHF<< Low frequency pole fLF
    A detailed analysis of discrete component selection to achieve a flat frequency response is discussed further in Section 9.1.