JAJSIG7D january   2020  – july 2023 CC2642R-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Functional Block Diagram
  6. 5 Revision History
  7. 6 Device Comparison
  8. 7 Terminal Configuration and Functions
    1. 7.1 Pin Diagram – RTC and RGZ Package (Top View)
    2. 7.2 Signal Descriptions
    3. 7.3 Connections for Unused Pins and Modules
  9. 8 Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Recommended Operating Conditions
    4. 8.4  Power Supply and Modules
    5. 8.5  Power Consumption - Power Modes
    6. 8.6  Power Consumption - Radio Modes
    7. 8.7  Nonvolatile (Flash) Memory Characteristics
    8. 8.8  Thermal Resistance Characteristics
    9. 8.9  Bluetooth Low Energy Receive (RX)
    10. 8.10 Bluetooth Low Energy - Transmit (TX)
    11. 8.11 Timing and Switching Characteristics
      1. 8.11.1 Reset Timing
      2. 8.11.2 Wakeup Timing
      3. 8.11.3 Clock Specifications
        1. 8.11.3.1 48 MHz Crystal Oscillator (XOSC_HF)
        2. 8.11.3.2 48 MHz RC Oscillator (RCOSC_HF)
        3. 8.11.3.3 2 MHz RC Oscillator (RCOSC_MF)
        4. 8.11.3.4 32.768 kHz Crystal Oscillator (XOSC_LF)
        5. 8.11.3.5 32 kHz RC Oscillator (RCOSC_LF)
      4. 8.11.4 Synchronous Serial Interface (SSI) Characteristics
        1. 8.11.4.1 Synchronous Serial Interface (SSI) Characteristics
        2.       34
      5. 8.11.5 UART
        1. 8.11.5.1 UART Characteristics
    12. 8.12 Peripheral Characteristics
      1. 8.12.1 ADC
        1.       Analog-to-Digital Converter (ADC) Characteristics
      2. 8.12.2 DAC
        1. 8.12.2.1 Digital-to-Analog Converter (DAC) Characteristics
      3. 8.12.3 Temperature and Battery Monitor
        1. 8.12.3.1 Temperature Sensor
        2. 8.12.3.2 Battery Monitor
      4. 8.12.4 Comparators
        1. 8.12.4.1 Continuous Time Comparator
        2. 8.12.4.2 Low-Power Clocked Comparator
      5. 8.12.5 Current Source
        1. 8.12.5.1 Programmable Current Source
      6. 8.12.6 GPIO
        1. 8.12.6.1 GPIO DC Characteristics
    13. 8.13 Typical Characteristics
      1. 8.13.1 MCU Current
      2. 8.13.2 RX Current
      3. 8.13.3 TX Current
      4. 8.13.4 RX Performance
      5. 8.13.5 TX Performance
      6. 8.13.6 ADC Performance
  10. 9 Detailed Description
    1. 9.1  Overview
    2. 9.2  System CPU
    3. 9.3  Radio (RF Core)
      1. 9.3.1 Bluetooth 5 low energy
    4. 9.4  Memory
    5. 9.5  Sensor Controller
    6. 9.6  Cryptography
    7. 9.7  Timers
    8. 9.8  Serial Peripherals and I/O
    9. 9.9  Battery and Temperature Monitor
    10. 9.10 µDMA
    11. 9.11 Debug
    12. 9.12 Power Management
    13. 9.13 Clock Systems
    14. 9.14 Network Processor
  11. 10Application, Implementation, and Layout
    1. 10.1 Reference Designs
    2. 10.2 Junction Temperature Calculation
  12. 11Device and Documentation Support
    1. 11.1 Device Nomenclature
    2. 11.2 Tools and Software
      1. 11.2.1 SimpleLink™ Microcontroller Platform
    3. 11.3 Documentation Support
    4. 11.4 サポート・リソース
    5. 11.5 Trademarks
    6. 11.6 静電気放電に関する注意事項
    7. 11.7 用語集
  13. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.7 Nonvolatile (Flash) Memory Characteristics

Over operating free-air temperature range and VDDS = 3.0 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Flash sector size 8 KB
Supported flash erase cycles before failure, full bank(1) 30 k Cycles
Supported flash erase cycles before failure, single sector(2) 60 k Cycles
Maximum number of write operations per row before sector erase(3) 83 Write Operations
Flash retention 105 °C 11.4 Years at 105 °C
Flash sector erase current Average delta current 10.7 mA
Flash sector erase time(4) Zero cycles 10 ms
Flash sector erase time(4) 30k cycles 4000 ms
Flash write current Average delta current, 4 bytes at a time
 6.2 mA
Flash write time 4 bytes at a time 21.6 µs
(1) A full bank erase is counted as a single erase cycle on each sector
(2) Up to 4 customer-designated sectors can be individually erased an additional 30k times beyond the baseline bank limitation of 30k cycles
(3) Each wordline is 2048 bits (or 256 bytes) wide. This limitation corresponds to sequential memory writes of 4 (3.1) bytes minimum per write over a whole wordline. If additional writes to the same wordline are required, a sector erase is required once the maximum number of write operations per row is reached.
(4) This number is dependent on Flash aging and increases over time and erase cycles