JAJSND6D November   1997  – November 2021 CD54HC259 , CD54HCT259 , CD74HC259 , CD74HCT259

PRODUCTION DATA  

  1. 特長
  2. 概要
  3. Revision History
  4. Pin Configuration and Functions
  5. Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 Recommended Operating Conditions
    3. 5.3 Thermal Information
    4. 5.4 Electrical Characteristics
    5. 5.5 Prerequisite for Switching Characteristics
    6. 5.6 Switching Characteristics (2)
  6. Parameter Measurement Information
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Device Functional Modes
  8. Power Supply Recommendations
  9. Layout
    1. 9.1 Layout Guidelines
  10. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 サポート・リソース
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ(パッケージ|ピン)
  • J|16
サーマルパッド・メカニカル・データ
発注情報

Overview

The CDx4HC(T)259 8-bit addressable latches are designed for general-purpose storage applications in digital systems. Specific uses include working registers, serial-holding registers, and active-high decoders or demultiplexers. They are multifunctional devices capable of storing single-line data in eight addressable latches and being a 1-of-8 decoder or demultiplexer with active-high outputs.

Four distinct modes of operation are selectable by controlling the clear (CLR) and enable (G) inputs:

  • Addressable-latch mode: CLR = HIGH; G = LOW
    • Data at the data-in terminal is written into the addressed latch
    • The addressed latch follows the data input, with all unaddressed latches remaining in their previous states
  • Memory mode: CLR = HIGH; G = HIGH
    • All latches remain in their previous states and are unaffected by the data or address inputs
    • To eliminate the possibility of entering erroneous data in the latches, G should be held high (inactive) while the address lines are changing
  • 1-of-8 decoding or demultiplexing mode: CLR = LOW; G = LOW
    • The addressed output follows the level of the D input with all other outputs low
  • Clear mode: CLR = LOW; G = HIGH
    • All outputs are low and unaffected by the address and data inputs