JAJSRL8H June   2007  – February 2024 CDCE913 , CDCEL913

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 EEPROM Specification
    7. 5.7 Timing Requirements: CLK_IN
    8. 5.8 Timing Requirements: SDA/SCL
    9. 5.9 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Control Terminal Configuration
      2. 7.3.2 Default Device Configuration
      3. 7.3.3 SDA/SCL Serial Interface
      4. 7.3.4 Data Protocol
    4. 7.4 Device Functional Modes
      1. 7.4.1 SDA/SCL Hardware Interface
    5. 7.5 Programming
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Spread-Spectrum Clock (SSC)
        2. 8.2.2.2 PLL Frequency Planning
        3. 8.2.2.3 Crystal Oscillator Start-up
        4. 8.2.2.4 Frequency Adjustment with Crystal Oscillator Pulling
        5. 8.2.2.5 Unused Inputs/Outputs
        6. 8.2.2.6 Switching Between XO and VCXO Mode
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Register Maps
    1. 9.1 SDA/SCL Configuration Registers
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 ドキュメントの更新通知を受け取る方法
    3. 10.3 サポート・リソース
    4. 10.4 Trademarks
    5. 10.5 静電気放電に関する注意事項
    6. 10.6 用語集
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5.5 Electrical Characteristics

over recommended operating free-air temperature range (unless otherwise noted)
TEST CONDITIONSMINTYP(1)MAXUNIT
OVERALL PARAMETER
IDDSupply current (see Figure 5-1)All outputs off, fCLK = 27 MHz,
fVCO = 135 MHz;
fOUT = 27 MHz		All PLLS on11mA
Per PLL9
IDD(OUT)Supply current (see Figure 5-2 and Figure 5-3)No load, all outputs on,
fOUT = 27 MHz		VDDOUT = 3.3 V1.3mA
VDDOUT = 1.8 V0.7
IDD(PD)Power-down current. Every circuit powered down except SDA/SCLfIN = 0 MHz, VDD = 1.9 V30μA
V(PUC)Supply voltage Vdd threshold for power-up control circuit0.851.45V
fVCOVCO frequency range of PLL80230MHz
fOUTLVCMOS output frequencyVDDOUT = 3.3 V230MHz
VDDOUT = 1.8 V230
LVCMOS PARAMETER
VIKLVCMOS input voltageVDD = 1.7 V; II = –18 mA–1.2V
IILVCMOS input currentVI = 0 V or VDD; VDD = 1.9 V±5μA
IIHLVCMOS input current for S0/S1/S2VI = VDD; VDD = 1.9 V5μA
IILLVCMOS input current for S0/S1/S2VI = 0 V; VDD = 1.9 V–4μA
CIInput capacitance at Xin/ClkVIClk = 0 V or VDD6pF
Input capacitance at XoutVIXout = 0 V or VDD2
Input capacitance at S0/S1/S2VIS = 0 V or VDD3
CDCE913 - LVCMOS PARAMETER FOR VDDOUT = 3.3 V – MODE
VOHLVCMOS high-level output voltageVDDOUT = 3 V, IOH = –0.1 mA2.9V
VDDOUT = 3 V, IOH = –8 mA2.4
VDDOUT = 3 V, IOH = –12 mA2.2
VOLLVCMOS low-level output voltageVDDOUT = 3 V, IOL = 0.1 mA0.1V
VDDOUT = 3 V, IOL = 8 mA0.5
VDDOUT = 3 V, IOL = 12 mA0.8
tPLH, tPHLPropagation delayPLL bypass3.2ns
tr/tfRise and fall timeVDDOUT = 3.3 V (20%–80%)0.6ns
tjit(cc)Cycle-to-cycle jitter(2)(3)1 PLL switching, Y2-to-Y35070ps
tjit(per)Peak-to-peak period jitter(3)1 PLL switching, Y2-to-Y360100ps
tsk(o)Output skew (4), See Table 7-2fOUT = 50 MHz; Y1-to-Y360ps
odcOutput duty cycle (5)fVCO = 100 MHz; Pdiv = 145%55%
CDCE913 – LVCMOS PARAMETER for VDDOUT = 2.5 V – MODE
VOHLVCMOS high-level output voltageVDDOUT = 2.3 V, IOH = –0.1 mA2.2V
VDDOUT = 2.3 V, IOH = –6 mA1.7
VDDOUT = 2.3 V, IOH = –10 mA1.6
VOLLVCMOS low-level output voltageVDDOUT = 2.3 V, IOL = 0.1 mA0.1V
VDDOUT = 2.3 V, IOL = 6 mA0.5
VDDOUT = 2.3 V, IOL = 10 mA0.7
tPLH, tPHLPropagation delayPLL bypass3.6ns
tr/tfRise and fall timeVDDOUT = 2.5 V (20%–80%)0.8ns
tjit(cc)Cycle-to-cycle jitter(2)(3)1 PLL switching, Y2-to-Y35070ps
tjit(per)Peak-to-peak period jitter(3)1 PLL switching, Y2-to-Y360100ps
tsk(o)Output skew(4) , See Table 7-2fOUT = 50 MHz; Y1-to-Y360ps
odcOutput duty cycle(5)fVCO = 100 MHz; Pdiv = 145%55%
CDCEL913 — LVCMOS PARAMETER for VDDOUT = 1.8 V – MODE
VOHLVCMOS high-level output voltageVDDOUT = 1.7 V, IOH = –0.1 mA1.6V
VDDOUT = 1.7 V, IOH = –4 mA1.4
VDDOUT = 1.7 V, IOH = –8 mA1.1
VOLLVCMOS low-level output voltageVDDOUT = 1.7 V, IOL = 0.1 mA0.1V
VDDOUT = 1.7 V, IOL = 4 mA0.3
VDDOUT = 1.7 V, IOL = 8 mA0.6
tPLH, tPHLPropagation delayPLL bypass2.6ns
tr/tfRise and fall timeVDDOUT = 1.8 V (20%–80%)0.7ns
tjit(cc)Cycle-to-cycle jitter(2)(3)1 PLL switching, Y2-to-Y380110ps
tjit(per)Peak-to-peak period jitter(3)1 PLL switching, Y2-to-Y3100130ps
tsk(o)Output skew(4), See Table 7-2fOUT = 50 MHz; Y1-to-Y350ps
odcOutput duty cycle(5)fVCO = 100 MHz; Pdiv = 145%55%
SDA/SCL PARAMETER
VIKSCL and SDA input clamp voltageVDD = 1.7 V; II = –18 mA–1.2V
IIHSCL and SDA input currentVI = VDD; VDD = 1.9 V±10μA
VIHSDA/SCL input high voltage(6)0.7 × VDDV
VILSDA/SCL input low voltage(6)0.3 × VDDV
VOLSDA low-level output voltageIOL = 3 mA, VDD = 1.7 V0.2 × VDDV
CISCL/SDA input capacitanceVI = 0 V or VDD310pF
(1) All typical values are at respective nominal VDD.
(2) 10,000 cycles.
(3) Jitter depends on configuration. Jitter data is for input frequency = 27 MHz, fVCO = 108 MHz, fOUT = 27 MHz (measured at Y2).
(4) The tsk(o) specification is only valid for equal loading of each bank of outputs, and the outputs are generated from the same divider.
(5) odc depends on output rise and fall time (tr/tf); data sampled on rising edge (tr)
(6) SDA and SCL pins are 3.3-V tolerant.