SCAS884D August   2009  – December 2015 CDCLVP1102

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics: LVCMOS Input
    6. 6.6 Electrical Characteristics: Differential Input
    7. 6.7 Electrical Characteristics: LVPECL Output
    8. 6.8 Electrical Characteristics: LVPECL Output
    9. 6.9 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Test Configurations
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
      1. 8.4.1 LVPECL Output Termination
      2. 8.4.2 Input Termination
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Fanout Buffer for Line Card Application
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Thermal Considerations
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

9.1 Application Information

The CDCLVP1102 is a low additive jitter LVPECL fanout buffer that can generate two copies of a LVPECL, LVDS, or LVCMOS input. The CDCLVP1102 can accept reference clock frequencies up to 2 GHz while providing low output skew.

9.2 Typical Application

9.2.1 Fanout Buffer for Line Card Application

CDCLVP1102 typical_application_1102.gif Figure 20. CDCLVP1102 Typical Application

9.2.1.1 Design Requirements

The CDCLVP1102 shown in Figure 20 is configured to receive a 156.25-MHz LVPECL clock from the backplane. Either signal can be then fanned out to desired devices, as shown. The configuration example is driving 2 LVPECL receivers in a line card application with the following properties:

  • The PHY device has internal AC coupling and appropriate termination and biasing. The CDCLVP1102 will need to be provided with 86-Ω emitter resistors near the driver for proper operation.
  • The ASIC is capable of DC coupling with a 2.5-V LVPECL driver such as the CDCLVP1102. This ASIC features internal termination so no additional components are needed.

9.2.1.2 Detailed Design Procedure

Refer to Input Termination for proper input terminations, dependent on single ended or differential inputs.

Refer to LVPECL Output Termination for output termination schemes depending on the receiver application. Unused outputs can be left floating.

In this example, the PHY, ASIC, and FPGA/CPU require different schemes. Power supply filtering and bypassing is critical for low noise applications.

See Power Supply Recommendations for recommended filtering techniques. A reference layout is provided on the CDCLVP1102 Evaluation Module at SCAU035.

9.2.1.3 Application Curves

The CDCLVP1102's low additive noise can be shown in this line card application. The low noise 156.25 MHz XO with 32-fs RMS jitter drives the CDCLVP1102, resulting in 57-fs RMS when integrated from 10 kHz to 20 MHz. The resultant additive jitter is a low 47-fs RMS for this configuration.

CDCLVP1102 ref_noise_1102.png
Figure 21. CDCLVP1102 Reference Phase Noise 32 fs rms (10 kHz to 20 MHz)
CDCLVP1102 output_noise_1102.png
Figure 22. CDCLVP1102 Output Phase Noise 57 fs rms (10 kHz to 20 MHz)