SCAS884D August   2009  – December 2015 CDCLVP1102

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics: LVCMOS Input
    6. 6.6 Electrical Characteristics: Differential Input
    7. 6.7 Electrical Characteristics: LVPECL Output
    8. 6.8 Electrical Characteristics: LVPECL Output
    9. 6.9 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Test Configurations
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
      1. 8.4.1 LVPECL Output Termination
      2. 8.4.2 Input Termination
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Fanout Buffer for Line Card Application
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Thermal Considerations
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VCC Supply voltage range(2) –0.5 4.6 V
VIN Input voltage range (3) –0.5 VCC + 0.5 V
VOUT Output voltage range (3) –0.5 VCC + 0.5 V
IIN Input current 20 mA
IOUT Output current 50 mA
TA Specified free-air temperature (no airflow) –40 85 °C
TJ Maximum junction temperature 125 °C
Tstg Storage temperature –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All supply voltages must be supplied simultaneously.
(3) The input and output negative voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VCC Supply voltage 2.375 2.50/3.30 3.60 V
TA Ambient temperature –40 85 °C
TPCB PCB temperature (measured at thermal pad) 105 °C

6.4 Thermal Information

THERMAL METRIC(1)(2)(3) CDCLVP1102 UNIT
RGT (VQFN)
16 PINS
RθJA Junction-to-ambient thermal resistance 0 LFM(4) 51.8 °C/W
150 LFM(4) 45
400 LFM(4) 40.8
RθJC(top) Junction-to-case (top) thermal resistance 61.3 °C/W
RθJB(5) Junction-to-board thermal resistance 21.7 °C/W
ψJT Junction-to-top characterization parameter 1.5 °C/W
ψJB Junction-to-board characterization parameter 21.7 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 6.3 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report (SPRA953).
(2) The package thermal resistance is calculated in accordance with JESD 51 and JEDEC 2S2P (high-K board).
(3) Connected to GND with four thermal vias (0.3-mm diameter).
(4) 2 x 2 vias on Pad
(5) θJP (junction-to-pad) is used for the QFN package, because the primary heat flow is from the junction to the GND pad of the QFN package.

6.5 Electrical Characteristics: LVCMOS Input

at VCC = 2.375 V to 3.6 V and TA = –40°C to 85°C and TPCB ≤ 105°C (unless otherwise noted)(1)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
fIN Input frequency 200 MHz
Vth Input threshold voltage External threshold voltage applied to complementary input 1.1 1.8 V
VIH Input high voltage Vth + 0.1 VCC V
VIL Input low voltage 0 Vth – 0.1 V
IIH Input high current VCC = 3.6 V, VIH = 3.6 V 40 μA
IIL Input low current VCC = 3.6 V, VIL = 0 V –40 μA
ΔV/ΔT Input edge rate 20% to 80% 1.5 V/ns
ICAP Input capacitance 5 pF
(1) Figure 3 and Figure 4 show DC test setup.

6.6 Electrical Characteristics: Differential Input

at VCC = 2.375 V to 3.6 V and TA = –40°C to 85°C and TPCB ≤ 105°C (unless otherwise noted)(1)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
fIN Input frequency Clock input 2000 MHz
VIN, DIFF, PP Differential input peak-peak voltage fIN ≤ 1.5 GHz 0.1 1.5 V
1.5 GHz ≤ fIN ≤ 2 GHz 0.2 1.5 V
VICM Input common-mode level 1 VCC – 0.3 V
IIH Input high current VCC = 3.6 V, VIH = 3.6 V 40 μA
IIL Input low current VCC = 3.6 V, VIL = 0 V –40 μA
ΔV/ΔT Input edge rate 20% to 80% 1.5 V/ns
ICAP Input capacitance 5 pF
(1) Figure 5 and Figure 6 show DC test setup. Figure 7 shows AC test setup.

6.7 Electrical Characteristics: LVPECL Output

at VCC = 2.375 V to 2.625 V and TA = –40°C to 85°C and TPCB ≤ 105°C (unless otherwise noted)(1)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOH Output high voltage TA ≤ 85ºC VCC – 1.26 VCC – 0.9 V
TPCB ≤ 105ºC VCC – 1.26 VCC – 0.83 V
VOL Output low voltage TA ≤ 85ºC VCC – 1.7 VCC – 1.3 V
TPCB ≤ 105ºC VCC – 1.7 VCC – 1.25 V
VOUT, DIFF, PP Differential output peak-peak voltage fIN ≤ 2 GHz 0.5 1.35 V
VAC_REF Input bias voltage(2) IAC_REF = 2 mA VCC – 1.6 VCC – 1.1 V
tPD Propagation delay VIN, DIFF, PP = 0.1 V 450 ps
VIN, DIFF, PP = 0.3 V 450 ps
tSK,PP Part-to-part skew 100 ps
tSK,O Output skew 10 ps
tSK,P Pulse skew (with 50% duty cycle input) Crossing-point-to-crossing-point distortion, fOUT = 100 MHz –50 50 ps
fOUT = 100 MHz, VIN,SE = VCC,
Vth = 1.25 V, 10 kHz to 20 MHz		 0.089 ps, RMS
fOUT = 100 MHz, VIN,SE = 0.9 V,
Vth = 1.1 V, 10 kHz to 20 MHz		 0.093 ps, RMS
tRJIT Random additive jitter (with 50% duty cycle input) fOUT = 2 GHz, VIN,DIFF,PP = 0.2 V,
VICM = 1 V, 10 kHz to 20 MHz		 0.037 ps, RMS
fOUT = 100 MHz, VIN,DIFF,PP = 0.15 V,
VICM = 1 V, 10 kHz to 20 MHz		 0.094 ps, RMS
fOUT = 100 MHz, VIN,DIFF,PP = 1 V,
VICM = 1 V, 10 kHz to 20 MHz		 0.091 ps, RMS
tR/tF Output rise/fall time 20% to 80% 200 ps
IEE Supply internal current Outputs unterminated,
TA ≤ 85ºC		 33 mA
Outputs unterminated,
TPCB ≤ 105ºC		 34 mA
ICC Output and internal supply current All outputs terminated, 50 Ω to VCC – 2,
TA ≤ 85ºC		 100 mA
All outputs terminated, 50 Ω to VCC – 2,
TPCB ≤ 105ºC		 105 mA
(1) Figure 8 and Figure 9 show DC and AC test setup.
(2) Internally generated bias voltage (VAC_REF) is for 3.3-V operation only. It is recommended to apply externally generated bias voltage for VCC < 3.0 V.

6.8 Electrical Characteristics: LVPECL Output

at VCC = 3.0 V to 3.6 V and TA = –40°C to 85°C and TPCB ≤ 105°C (unless otherwise noted)(1)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOH Output high voltage TA ≤ 85ºC VCC – 1.26 VCC – 0.9 V
TPCB ≤ 105ºC VCC – 1.26 VCC – 0.85 V
VOL Output low voltage TA ≤ 85ºC VCC – 1.7 VCC – 1.3 V
TPCB ≤ 105ºC VCC – 1.7 VCC – 1.3 V
VOUT, DIFF, PP Differential output peak-peak voltage fIN ≤ 2 GHz 0.65 1.35 V
VAC_REF Input bias voltage IAC_REF = 2 mA VCC – 1.6 VCC – 1.1 V
tPD Propagation delay VIN, DIFF, PP = 0.1 V 450 ps
VIN, DIFF, PP = 0.3 V 450 ps
tSK,PP Part-to-part skew 100 ps
tSK,O Output skew 10 ps
tSK,P Pulse skew (with 50% duty cycle input) Crossing-point-to-crossing-point distortion, fOUT = 100 MHz –50 50 ps
tRJIT Random additive jitter (with 50% duty cycle input) fOUT = 100 MHz, VIN,SE = VCC,
Vth = 1.65 V, 10 kHz to 20 MHz		 0.081 ps, RMS
fOUT = 100 MHz, VIN,SE = 0.9 V,
Vth = 1.1 V, 10 kHz to 20 MHz		 0.097
fOUT = 2 GHz, VIN,DIFF,PP = 0.2 V,
VICM = 1 V, 10 kHz to 20 MHz		 0.050
fOUT = 100 MHz, VIN,DIFF,PP = 0.15 V,
VICM = 1 V, 10 kHz to 20 MHz		 0.098
fOUT = 100 MHz, VIN,DIFF,PP = 1 V,
VICM = 1 V, 10 kHz to 20 MHz		 0.095
tR/tF Output rise/fall time 20% to 80% 200 ps
IEE Supply internal current Outputs unterminated,
TA ≤ 85ºC		 33 mA
Outputs unterminated,
TPCB ≤ 105ºC		 34 mA
ICC Output and internal supply current All outputs terminated, 50 Ω to VCC – 2,
TA ≤ 85ºC		 100 mA
All outputs terminated, 50 Ω to VCC – 2,
TPCB ≤ 105ºC		 105 mA
(1) Figure 8 and Figure 9 show DC and AC test setup.

6.9 Typical Characteristics

at TA = –40°C to 85°C (unless otherwise noted)
CDCLVP1102 tc_fqcy_diff_vout_swing01_cas884.gif
Figure 1. Differential Output Peak-To-Peak Voltage vs Frequency
CDCLVP1102 tc_fqcy_diff_vout_swing02_cas884.gif
Figure 2. Differential Output Peak-To-Peak Voltage vs Frequency