SLPS542 January   2015 CSD97394Q4M

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
  7. 7 Electrical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Powering CSD97394Q4M And Gate Drivers
      2. 8.3.2 Undervoltage Lockout Protection (UVLO)
      3. 8.3.3 PWM Pin
      4. 8.3.4 SKIP# Pin
        1. 8.3.4.1 Zero Crossing (ZX) Operation
      5. 8.3.5 Integrated Boost-Switch
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Application Curves
  10. 10System Example
    1. 10.1 Power Loss Curves
    2. 10.2 Safe Operating Curves (SOA)
    3. 10.3 Normalized Curves
      1. 10.3.1 Calculating Power Loss and SOA
        1. 10.3.1.1 Design Example
        2. 10.3.1.2 Calculating Power Loss
        3. 10.3.1.3 Calculating SOA Adjustments
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Recommended PCB Design Overview
      2. 11.1.2 Electrical Performance
    2. 11.2 Layout Example
    3. 11.3 Thermal Considerations
  12. 12Device and Documentation Support
    1. 12.1 Trademarks
    2. 12.2 Electrostatic Discharge Caution
    3. 12.3 Glossary
  13. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Mechanical Drawing
    2. 13.2 Recommended PCB Land Pattern
    3. 13.3 Recommended Stencil Opening

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
  • DPC|8
サーマルパッド・メカニカル・データ
発注情報

9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

9.1 Application Information

The Power Stage CSD97394Q4M is a highly optimized design for synchronous buck applications using NexFET devices with a 5 V gate drive. The Control FET and Sync FET silicon are parametrically tuned to yield the lowest power loss and highest system efficiency. As a result, a rating method is used that is tailored towards a more systems centric environment. The high-performance gate driver IC integrated in the package helps minimize the parasitics and results in extremely fast switching of the power MOSFETs. System level performance curves such as Power Loss, Safe Operating Area and normalized graphs allow engineers to predict the product performance in the actual application.

9.2 Typical Application

application_diagram_CSD97394.gifFigure 3. Application Schematic

9.2.1 Application Curves

TJ = 125°C, unless stated otherwise
D002_SLPS542.gif
VIN = 12 V VDD = 5 V VOUT = 1.8 V
ƒSW = 500 kHz LOUT = 0.29 µH
Figure 4. Power Loss vs Output Current
D004_SLPS542.gif
VIN = 12 V VDD = 5 V VOUT = 1.8 V
ƒSW = 500 kHz LOUT = 0.29 µH
Figure 6. Safe Operating Area – PCB Horizontal Mount (1)
D006_SLPS542.gif
VIN = 12 V VDD = 5 V VOUT = 1.8 V
ƒSW = 500 kHz LOUT = 0.29 µH
Figure 8. Typical Safe Operating Area (1)
D008_SLPS542.gif
IOUT = 20 A VDD = 5 V VOUT = 1.8 V
ƒSW = 500 kHz LOUT = 0.29 µH
Figure 10. Normalized Power Loss vs Input Voltage
D010_SLPS542.gif
VIN = 12 V VDD = 5 V IOUT = 20 A
ƒSW = 500 kHz VOUT = 1.8 V
Figure 12. Normalized Power Loss vs Output Inductance
D012_SLPS542.gif
VIN = 12 V VDD = 5 V VOUT = 1.8 V
IOUT = 20 A LOUT = 0.29 µH
Figure 14. Driver Current vs Temperature
D003_SLPS542.gif
VIN = 12 V VDD = 5 V VOUT = 1.8 V
ƒSW = 500 kHz LOUT = 0.29 µH
Figure 5. Power Loss vs Temperature
D005_SLPS542.gif
VIN = 12 V VDD = 5 V VOUT = 1.8 V
ƒSW = 500 kHz LOUT = 0.29 µH
Figure 7. Safe Operating Area – PCB Vertical Mount (1)
D007_SLPS542.gif
VIN = 12 V VDD = 5 V VOUT = 1.8 V
IOUT = 20 A LOUT = 0.29 µH
Figure 9. Normalized Power Loss vs Frequency
D009_SLPS542.gif
VIN = 12 V VDD = 5 V IOUT = 20 A
ƒSW = 500 kHz LOUT = 0.29 µH
Figure 11. Normalized Power Loss vs Output Voltage
D011_SLPS542.gif
VIN = 12 V VDD = 5 V IOUT = 20 A
LOUT = 0.29 µH VOUT = 1.8 V
Figure 13. Driver Current vs Frequency
  1. The Typical CSD97394Q4M System Characteristic curves are based on measurements made on a PCB design with dimensions of 4.0 inches (W) × 3.5 inches (L) × 0.062 inch (T) and 6 copper layers of 1 oz. copper thickness. See the System Example section for detailed explanation.