JAJSPG6B December 2022 – February 2024 DLP4620S-Q1
PRODUCTION DATA
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MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|
SUPPLY VOLTAGE | |||||
VDD | Supply voltage for LVCMOS core logic Supply voltage for LPSDR low-speed interface |
1.65 | 1.8 | 1.95 | V |
VDDI | Supply voltage for SubLVDS receivers | 1.65 | 1.8 | 1.95 | V |
VOFFSET | Supply voltage for HVCMOS and micromirror electrode(3) | 8.25 | 8.5 | 8.75 | V |
VBIAS | Supply voltage for mirror electrode | 15.5 | 16 | 16.5 | V |
VRESET | Supply voltage for micromirror electrode | –9.5 | –10 | –10.5 | V |
|VDDI – VDD| | Supply voltage delta (absolute value)(4) | 0.3 | V | ||
|VBIAS – VOFFSET| | Supply voltage delta (absolute value)(5) | 8.75 | V | ||
|VBIAS – VRESET| | Supply voltage delta (absolute value)(6) | 28 | V | ||
LOW-SPEED LPDSR INTERFACE | |||||
fclock_LS | Clock frequency for low speed interface LS_CLK | 108 | 120 | MHz | |
DCDIN | LSIF duty cycle distortion (LS_CLK) | 44% | 56% | — | |
SUBLVDS INTERFACE | |||||
fclock_HS | Clock frequency for high-speed interface DCLK | 300 | 540 | MHz | |
DCDIN | LVDS duty cycle distortion (DCLK) | 44% | 56% | — | |
|VID| | LVDS differential input voltage magnitude(7) | 150 | 250 | 350 | mV |
VCM | Common mode voltage(7) | 700 | 900 | 1100 | mV |
VSUBLVDS | SubLVDS voltage(7) | 525 | 1275 | mV | |
ZLINE | Line differential impedance (PWB/trace) | 90 | 100 | 110 | Ω |
ZIN | Internal differential termination resistance (8) | 80 | 100 | 120 | Ω |
100Ω differential PCD trace | 6.35 | 152.4 | mm | ||
ENVIRONMENTAL | |||||
TARRAY | Array Temperature(9)(11) | –40 | 105 | °C | |
Illumination | |||||
ILLUV | Illumination, wavelength < 395nm(10) | 2 | mW/cm2 | ||
ILLOVERFILL | Illumination overfill maximum heat load in the area shown in the Illumination Overfill Diagram. | 90 | mW/mm2 |