JAJSPG6 データシート

JAJSPG6B December 2022 – February 2024 DLP4620S-Q1

PRODUCTION DATA

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）

FQX|120

サーマルパッド・メカニカル・データ

発注情報

5.7 Timing Requirements

Device electrical characteristics are over Recommended Operating ConditionsRecommended Operating ConditionsRecommended Operating ConditionsRecommended Operating Conditions unless otherwise noted

			MIN	NOM	MAX	UNIT
Low-Speed Interface
t_r	Rise slew rate⁽¹⁾⁽²⁾	(20% to 80%) × VDD	0.25			V/ns
t_f	Fall slew rate⁽¹⁾⁽²⁾	(80% to 20%) × VDD	0.25			V/ns
t_c	Cycle time LS_CLK		7.7	8.3		ns
t_W(H)	Pulse duration LS_CLK high⁽³⁾	50% to 50% reference points	3.1			ns
t_W(L)	Pulse duration LS_CLK low⁽³⁾	50% to 50% reference points	3.1			ns
t_su	Setup time⁽³⁾	LS_WDATA valid before LS_CLK↑ or LS_CLK↓	1.5			ns
t_h	Hold time⁽³⁾	LS_WDATA valid after LS_CLK↑ or LS_CLK↓	1.5			ns
t_WINDOW	Window time	Setup time + hold time	3			ns
t_DERATING	Window time derating	For each 0.25V/ns reduction in slew rate below 1V/ns		0.35		ns
High-Speed Interface
t_r	Rise slew rate⁽²⁾	20% to 80% reference points	0.7	1		V/ns
t_f	Fall slew rate⁽²⁾	80% to 20% reference points	0.7	1		V/ns
t_c	Cycle time DCLK ⁽³⁾		1.79	1.85		ns
t_W(H)	Pulse duration DCLK high⁽³⁾	50% to 50% reference points	0.79			ns
t_W(L)	Pulse duration DCLK low⁽³⁾	50% to 50% reference points	0.79			ns
t_WINDOW	Window time⁽³⁾⁽⁴⁾	Setup time + Hold time	0.3			ns
t_{LVDS-EN+REFGEN}	Power-up receiver⁽⁵⁾				2000	ns

(1) Specification is for DMD_DEN_ARSTZ pin. Refer to LPSDR input rise and fall slew rate in Figure 5-2.

(2) See Figure 5-3.

(3) See Figure 5-4.

(4) See Figure 5-5.

(5) Specification is for SubLVDS receiver time only and does not take into account commanding and latency after commanding.