JAJSOE9B april   2019  – march 2023 DLP470TE

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  Storage Conditions
    3. 6.3  ESD Ratings
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Thermal Information
    6. 6.6  Electrical Characteristics
    7. 6.7  Capacitance at Recommended Operating Conditions
    8. 6.8  Timing Requirements
      1. 6.8.1 Timing Diagrams
    9. 6.9  System Mounting Interface Loads
    10. 6.10 Micromirror Array Physical Characteristics
    11. 6.11 Micromirror Array Optical Characteristics
    12. 6.12 Window Characteristics
    13. 6.13 Chipset Component Usage Specification
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power Interface
      2. 7.3.2 Timing
    4. 7.4 Device Functional Modes
    5. 7.5 Optical Interface and System Image Quality Considerations
      1. 7.5.1 Numerical Aperture and Stray Light Control
      2. 7.5.2 Pupil Match
      3. 7.5.3 Illumination Overfill
    6. 7.6 Micromirror Array Temperature Calculation
    7. 7.7 Micromirror Landed-On/Landed-Off Duty Cycle
      1. 7.7.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
      2. 7.7.2 Landed Duty Cycle and Useful Life of the DMD
      3. 7.7.3 Landed Duty Cycle and Operational DMD Temperature
      4. 7.7.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 DMD Die Temperature Sensing
  9. 9 Power Supply Recommendations
    1. 9.1 DMD Power Supply Power-Up Procedure
    2. 9.2 DMD Power Supply Power-Down Procedure
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
      1. 10.2.1 Layers
      2. 10.2.2 Impedance Requirements
      3. 10.2.3 Trace Width, Spacing
        1. 10.2.3.1 Voltage Signals
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Device Nomenclature
      2. 11.1.2 Device Markings
    2. 11.2 サード・パーティ製品に関する免責事項
    3. 11.3 Documentation Support
      1. 11.3.1 Related Documentation
      2. 11.3.2 サポート・リソース
      3. 11.3.3 Receiving Notification of Documentation Updates
    4. 11.4 Trademarks
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 用語集
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.1 Application Information

Texas Instruments DLP® technology is a micro-electro-mechanical systems (MEMS) technology that modulates light using a digital micromirror device (DMD). The DMD is a spatial light modulator, which reflects incoming light from an illumination source to one of two directions, towards the projection optics or collection optics. The new TRP pixel with a higher tilt angle increases brightness performance and enables smaller system electronics for size constrained applications. Typical applications using the DLP470NE include home theater, digital signage, interactive displays, low-latency gaming displays, and portable smart displays.

The most recent class of chipsets from Texas Instruments is based on a breakthrough micromirror technology called TRP. With a smaller pixel pitch of 5.4 µm and increased tilt angle of 17 degrees, TRP chipsets enable higher resolution in a smaller form factor and enhanced image processing features while maintaining high optical efficiency. DLP chipsets are a great fit for any system that requires high resolution and high brightness displays. The following orderables have been replaced by the DLP470TE.

Device Information
PART NUMBER PACKAGE BODY SIZE (NOM)

Mechanical ICD

1910-5532B

 FXJ (257) 32.2 mm × 22.3 mm 2516207

1910-5537B

 FXJ (257) 32.2 mm × 22.3 mm 2516207

1910-553AB

 FXJ (257) 32.2 mm × 22.3 mm 2516207