JAJSGT9G April 2010 – January 2019 DLP5500
PRODUCTION DATA.
デバイスごとのパッケージ図は、PDF版データシートをご参照ください。
Signals should be routed to have a matched impedance of 50 Ω ±10% except for LVDS differential pairs (DMD_DAT_Xnn, DMD_DCKL_Xn, and DMD_SCTRL_Xn) and DDR2 differential clock pairs (MEM_CLK_nn), which should be matched to 100 Ω ±10% across each pair.