JAJSKY2A November   2017  – February 2023 DLP650LE

PRODUCTION DATA  

  1. 特長
  2. アプリケーション
  3. 概要
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  Storage Conditions
    3. 6.3  ESD Ratings
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Thermal Information
    6. 6.6  Electrical Characteristics
    7. 6.7  Capacitance at Recommended Operating Conditions
    8. 6.8  Timing Requirements
    9. 6.9  Window Characteristics
    10. 6.10 System Mounting Interface Loads
    11. 6.11 Micromirror Array Physical Characteristics
    12. 6.12 Micromirror Array Optical Characteristics
    13. 6.13 Chipset Component Usage Specification
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power Interface
      2. 7.3.2 Timing
    4. 7.4 Device Functional Modes
    5. 7.5 Optical Interface and System Image Quality Considerations
      1. 7.5.1 Numerical Aperture and Stray Light Control
      2. 7.5.2 Pupil Match
      3. 7.5.3 Illumination Overfill
    6. 7.6 Micromirror Array Temperature Calculation
    7. 7.7 Micromirror Landed-On/Landed-Off Duty Cycle
      1. 7.7.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
      2. 7.7.2 Landed Duty Cycle and Useful Life of the DMD
      3. 7.7.3 Landed Duty Cycle and Operational DMD Temperature
      4. 7.7.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
  9. Power Supply Recommendations
    1. 9.1 DMD Power Supply Power-Up Procedure
    2. 9.2 DMD Power Supply Power-Down Procedure
  10. 10Device and Documentation Support
    1. 10.1 サード・パーティ製品に関する免責事項
    2. 10.2 Device Support
      1. 10.2.1 Device Nomenclature
      2. 10.2.2 Device Markings
    3. 10.3 Documentation Support
      1. 10.3.1 Related Documentation
    4. 10.4 ドキュメントの更新通知を受け取る方法
    5. 10.5 サポート・リソース
    6. 10.6 Trademarks
    7. 10.7 静電気放電に関する注意事項
    8. 10.8 用語集
  11. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Absolute Maximum Ratings

Over operating free-air temperature range (unless otherwise noted).(1)
MINMAXUNIT
SUPPLY VOLTAGES
VCCSupply voltage for LVCMOS core logic(2)–0.54V
VCCISupply voltage for LVDS Interface(2)–0.54V
VOFFSETMicromirror Electrode and HVCMOS voltage(2)(3)–0.59V
VMBRSTInput voltage for MBRST(15:0)(2)–2828V
|VCCI – VCC|Supply voltage delta (absolute value)(4)0.3V
INPUT VOLTAGES
Input voltage for all other input pins(2)–0.5VCC + 0.3V
|VID|Input differential voltage (absolute value)(5)700mV
CLOCKS
ƒCLOCKClock frequency for LVDS interface, DCLK_A400MHz
ƒCLOCKClock frequency for LVDS interface, DCLK_B400MHz
ENVIRONMENTAL
TARRAY and TWINDOWTemperature, operating(6)090°C
Temperature, non–operating(6)–4090°C
|TDELTA|Absolute Temperature delta between any point on the window edge and the ceramic test point TP1(7)30°C
TDPDew point temperature, operating and non–operating (noncondensing)81°C
Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
All voltages are referenced to common ground VSS. VBIAS, VCC, VCCI, VOFFSET, and VRESET power supplies are all required for all DMD operating modes.
VOFFSET supply transients must fall within specified voltages.
Exceeding the recommended allowable voltage difference between VCC and VCCI may result in excessive current draw.
The maximum LVDS input voltage rating applies when each input of a differential pair is at the same voltage potential.
The highest temperature of the active array (as calculated using Section 7.6) or of any point along the window edge as defined in Figure 7-1. The locations of thermal test points TP2, TP3, TP4, and TP5 in Figure 7-1 are intended to measure the highest window edge temperature. If a particular application causes another point on the window edge to be at a higher temperature, then that point should be used.
Temperature delta is the highest difference between the ceramic test point 1 (TP1) and anywhere on the window edge as shown in Figure 7-1. The window test points TP2, TP3, TP4, and TP5 shown in Figure 7-1 are intended to result in the worst-case delta. If a particular application causes another point on the window edge to result in a larger delta temperature, then that point should be used.