JAJSO55 December 2022 DRV8317
PRODUCTION DATA
No protective action occurs after a VM under voltage warn event in this mode. The VM under voltage warn event is reported by driving the nFAULT pin low and setting the FAULT, UVW bits (in DEV_STS register) and VMUV_WARN bit (in SUP_STS register) to 1b. DRV8317 continues to operate as usual. The external controller manages the VM under voltage warn condition by acting appropriately. The reporting clears (nFAULT pin is released, FAULT, UVW and VMUV_WARN bits are set to 0b) when a clear fault command is issued either through the FLT_CLR bit or an nSLEEP reset pulse (tRST).