JAJSO55 December 2022 DRV8317
PRODUCTION DATA
After a VM under voltage warn event in this mode, all the FETs are in Hi-Z and the nFAULT pin is driven low. The FAULT, UVW bits (in DEV_STS register) and VMUV_WARN bit (in SUP_STS register) are set to 1b. Normal operation resumes automatically (pre-driver operation and the nFAULT pin is released) once the retry time (tRETRY) time lapses after the VM pin voltage rises above the VVMUV_WARN_RISE threshold as shown in Figure 8-24. The FAULT, UVW and VMUV_WARN bits stay set to 1b until clear fault command is issued either through the FLT_CLR bit or an nSLEEP reset pulse (tRST).
Retry time (tRETRY) is set by,