SLRS065E September   2013  – November 2015 DRV8860

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Simplified Schematic
  5. 5 Revision History
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 Handling Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Recommended Output Current
      2. 8.3.2 Daisy Chain Connection
      3. 8.3.3 Protection Circuits
        1. 8.3.3.1 Overcurrent Protection (OCP)
        2. 8.3.3.2 Open Load Detection (OL) - DRV8860 only
        3. 8.3.3.3 Thermal Shutdown (TSD)
        4. 8.3.3.4 Undervoltage Lockout (UVLO)
        5. 8.3.3.5 Digital Noise Filter
    4. 8.4 Device Functional Modes
      1. 8.4.1 Internal Registers
    5. 8.5 Programming
      1. 8.5.1 Serial Control Interface
        1. 8.5.1.1 Data Writing Waveform
        2. 8.5.1.2 Fault Register Reading Waveform
        3. 8.5.1.3 Special Command
          1. 8.5.1.3.1 Special command: Write Control Register
          2. 8.5.1.3.2 Special command: Read Control Register
          3. 8.5.1.3.3 Special command: Read Data Register
          4. 8.5.1.3.4 Special command: Fault Register Reset
          5. 8.5.1.3.5 Special command: PWM Start
        4. 8.5.1.4 Output Energizing and PWM Control
          1. 8.5.1.4.1 PWM Start Special Command Used
    6. 8.6 Register Maps
      1. 8.6.1 Data Register
      2. 8.6.2 Fault Register
      3. 8.6.3 Control Register
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Drive Current
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Power Supply and Logic Sequencing
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Thermal Consideration
      1. 11.3.1 Power Dissipation
      2. 11.3.2 Heatsinking
  12. 12Device and Documentation Support
    1. 12.1 Community Resources
    2. 12.2 Trademarks
    3. 12.3 Electrostatic Discharge Caution
    4. 12.4 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

11 Layout

11.1 Layout Guidelines

  • The VM pin should be bypassed to GND using a low-ESR ceramic bypass capacitor with a recommended value of 0.1-μF rated for VM.
  • This capacitor should be placed as close as possible to the VM pin on the device with a thick trace or ground plane connection to the device GND pin.
  • The VM pin must be bypassed to ground using and appropriate bulk capacitor. This component must be located close to the DRV8860.

11.2 Layout Example

Where the pull-up voltage (V3P3) is an external supply in the range of the recommended operating conditions for the digital open-drain outputs.

DRV8860 DRV8860A layout_slrs65.gif Figure 39. DRV8860 Layout

11.3 Thermal Consideration

The DRV8860 device has thermal shutdown (TSD) as described in the Thermal Shutdown (TSD) section. If the die temperature exceeds approximately 150°C, the device is disabled until the temperature drops to a safe level.

Any tendency of the device to enter TSD is an indication of either excessive power dissipation, insufficient heatsinking, or too high of an ambient temperature.

11.3.1 Power Dissipation

Power dissipation in the DRV8860 device is dominated by the power dissipated in the output FET resistance, RDS(on). Use the following equation to calculate the estimated average power dissipation of each output when running a driving a load.

Equation 2. PD = RDS(on) x IO 2

where

  • PD is the power dissipation of one channel
  • RDS(on) is the resistance of each FET
  • IO is the RMS output current being applied to each channel

IO is equal to the average current into the channel. Note that at startup, this current is much higher than normal running current; these peak currents and their duration must be also be considered.

The total device dissipation is the power dissipated in each channel added together.

The maximum amount of power that can be dissipated in the device is dependent on ambient temperature and heatsinking.

NOTE

RDS(on) increases with temperature, so as the device heats, the power dissipation increases. This fact must be taken into consideration when sizing the heatsink.

11.3.2 Heatsinking

The PowerPAD package uses an exposed pad to remove heat from the device. For proper operation, this pad must be thermally connected to copper on the PCB to dissipate heat. On a multi-layer PCB with a ground plane, this connection can be accomplished by adding a number of vias to connect the thermal pad to the ground plane.

On PCBs without internal planes, a copper area can be added on either side of the PCB to dissipate heat. If the copper area is on the opposite side of the PCB from the device, thermal vias are used to transfer the heat between top and bottom layers.

For details about how to design the PCB, refer to the TI application report, PowerPAD™ Thermally Enhanced Package (SLMA002), and the TI application brief, PowerPAD Made Easy™ (SLMA004), available at www.ti.com. In general, the more copper area that can be provided, the more power can be dissipated.