JAJSI38C october   2016  – december 2020 DS280MB810

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Description (continued)
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements – Serial Management Bus Interface
    7. 7.7 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Device Data Path Operation
      2. 8.3.2 AC-coupled Receiver Inputs
      3. 8.3.3 Signal Detect
      4. 8.3.4 2-Stage CTLE
      5. 8.3.5 Driver DC Gain Control
      6. 8.3.6 2x2 Cross-point Switch
      7. 8.3.7 Configurable SMBus Address
    4. 8.4 Device Functional Modes
      1. 8.4.1 SMBus Slave Mode Configuration
      2. 8.4.2 SMBus Master Mode Configuration (EEPROM Self Load)
    5. 8.5 Programming
      1. 8.5.1 Transfer of Data with the SMBus Interface
    6. 8.6 Register Maps
      1. 8.6.1 Register Types: Global, Shared, and Channel
      2. 8.6.2 Global Registers: Channel Selection and ID Information
      3. 8.6.3 Shared Registers
      4. 8.6.4 Channel Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Backplane and Mid-Plane Reach Extension
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
      2. 9.2.2 Front-Port Applications
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
        1. 9.2.3.1 Pattern Generator Characteristics
        2. 9.2.3.2 Equalizing Moderate Pre-Channel Loss
        3. 9.2.3.3 Equalizing High Pre-Channel Loss
        4. 9.2.3.4 Equalizing High Pre-Channel Loss and Moderate Post-Channel Loss
    3. 9.3 Initialization Set Up
  11. 10Power Supply Recommendations
  12. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Examples
      1. 11.2.1 Stripline Example
      2. 11.2.2 Microstrip Example
  13. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
  14. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

9.2.1.1 Design Requirements

For backplane, mid-plane, and chip-to-chip reach extension applications, use the guidelines in the table below.

DESIGN PARAMETERREQUIREMENT
AC coupling capacitorsGenerally not required. 220-nF AC coupling capacitors are included in the DS280MB810 package on the RX side.
Input channel insertion loss≥ 10 dB at 14 GHz as a rough guideline. For best performance, the input channel insertion loss should be greater than or equal to the equalizer boost setting used in the DS280MB810.
Output channel insertion lossDepends on downstream ASIC or FPGA SerDes capabilities. Should be ≥ 5 dB at 14 GHz as a rough guideline.
Total (input + output) channel insertion lossDepends on downstream ASIC or FPGA SerDes capabilities. The DS280MB810 can extend the reach between two ASICs by 17+ dB beyond the ASICs' normal capabilities.
Link partner TX launch amplitude800 mVPP to 1200 mVPP differential
Link partner TX FIR filterDepends on the channel loss.