JAJSOE2 September   2022 DS320PR822

PRODUCTION DATA  

  1. 特長
  2. アプリケーション
  3. 概要
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 DC Electrical Characteristics
    6. 6.6 High Speed Electrical Characteristics
    7. 6.7 SMBUS/I2C Timing Charateristics
    8. 6.8 Typical Characteristics
    9. 6.9 Typical Jitter Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Linear Equalization
      2. 7.3.2 Flat-Gain
      3. 7.3.3 Receiver Detect State Machine
      4. 7.3.4 Cross Point
    4. 7.4 Device Functional Modes
      1. 7.4.1 Active PCIe Mode
      2. 7.4.2 Active Buffer Mode
      3. 7.4.3 Standby Mode
    5. 7.5 Programming
      1. 7.5.1 Pin Mode
        1. 7.5.1.1 Five-Level Control Inputs
      2. 7.5.2 SMBUS/I2C Register Control Interface
        1. 7.5.2.1 Shared Registers
        2. 7.5.2.2 Channel Registers
      3. 7.5.3 SMBus/I 2 C Primary Mode Configuration (EEPROM Self Load)
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 UPI x24 Lane Cross-Point Configuration
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 サポート・リソース
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

SMBUS/I2C Register Control Interface

If MODE = L2 (SMBus/I2C Secondary control mode), then the DS320PR822 is configured through a standard I2C or SMBus interface that may operate up to 400 kHz. The secondary address of the DS320PR822 is determined by the pin strap settings on the ADDR1 and ADDR0 pins. Note: secondary addresses to access channels 0-3 (Bank 0) and channels 4-7 (Bank 1) are different. Channel Bank 1 has address which is Channel Bank 0 address +1. The sixteen possible secondary addresses for each channel bank of the DS320PR822 are provided in Table 7-5. In SMBus/I2C modes the SCL and SDA pins must be pulled up to a 3.3 V supply with a pull-up resistor. The value of the resistor depends on total bus capacitance. 4.7 kΩ is a good first approximation for a bus capacitance of 10 pF.

Table 7-5 SMBUS/I2C Secondary Address Settings
ADDR1ADDR07-bit Secondary Address Channels 0-3 (Bank 0)7-bit Secondary Address Channels 4-7 (Bank 1)
L0L00x180x19
L0L10x1A0x1B
L0L20x1C0x1D
L0L30x1E0x1F
L0L4ReservedReserved
L1L00x200x21
L1L10x220x23
L1L20x240x25
L1L30x260x27
L1L4ReservedReserved
L2L00x280x29
L2L10x2A0x2B
L2L20x2C0x2D
L2L30x2E0x2F
L2L4ReservedReserved
L3L00x300x31
L3L10x320x33
L3L20x340x35
L3L30x360x37
L3L4ReservedReserved

The DS320PR822 has two types of registers:

  • Shared Registers: these registers can be accessed at any time and are used for device-level configuration, status read back, control, or to read back the device ID information.
  • Channel Registers: these registers are used to control and configure specific features for each individual channel. All channels have the same register set and can be configured independent of each other or configured as a group through broadcast writes to Bank 0 or Bank 1.

The DS320PR822 features two banks of channels, Bank 0 (Channels 0-3) and Bank 1 (Channels 4-7), each featuring a separate register set and requiring a unique SMBus secondary address.

Channel Registers Base Address Channel Bank 0 Access Channel Bank 1 Access
0x00 Channel 0 registers Channel 4 registers
0x20 Channel 1 registers Channel 5 registers
0x40 Channel 2 registers Channel 6 registers
0x60 Channel 3 registers Channel 7 registers
0x80

Broadcast write channel Bank 0 registers,

read channel 0 registers

Broadcast write channel Bank 1 registers,

read channel 4 registers

0xA0

Broadcast write channel 0-1 registers,

read channel 0 registers

Broadcast write channel 4-5 registers,

read channel 4 registers

0xC0

Broadcast write channel 2-3 registers,

read channel 2 registers

Broadcast write channel 6-7 registers,

read channel 6 registers

0xE0 Bank 0 Share registers Bank 1 Share registers