JAJSGU7B September   2005  – January 2019 DS90LV027AH

PRODUCTION DATA.  

  1. 特長
  2. アプリケーション
  3. 概要
    1.     Device Images
      1.      チャネル 1 の機能図
      2.      チャネル 2 の機能図
  4. 改訂履歴
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. Parameter Measurement Information
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
      1. 8.3.1 DS90LV027AH Driver Functionality
      2. 8.3.2 Driver Output Voltage and Power-On Reset
      3. 8.3.3 Driver Offset
    4. 8.4 Device Functional Modes
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Driver Supply Voltage
        2. 9.2.2.2 Driver Bypass Capacitance
        3. 9.2.2.3 Driver Input Votlage
        4. 9.2.2.4 Driver Output Voltage
        5. 9.2.2.5 Interconnecting Media
        6. 9.2.2.6 PCB Transmission Lines
      3. 9.2.3 Termination Resistor
      4. 9.2.4 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Microstrip vs. Stripline Topologies
      2. 11.1.2 Dielectric Type and Board Construction
      3. 11.1.3 Recommended Stack Layout
      4. 11.1.4 Separation Between Traces
      5. 11.1.5 Crosstalk and Ground Bounce Minimization
      6. 11.1.6 Decoupling
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 関連資料
    2. 12.2 ドキュメントの更新通知を受け取る方法
    3. 12.3 コミュニティ・リソース
    4. 12.4 商標
    5. 12.5 静電気放電に関する注意事項
    6. 12.6 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Overview

The DS90LV027AH is a dual-channel, low-voltage differential signaling (LVDS) line driver with a balanced current source design. It operates from a single power supply that is nominally 3.3 V, but the supply can be as low as 3.0 V and as high as 3.6 V. The input signal to the DS90LV027AH is an LVCMOS/LVTTL signal. The output of the device is a differential signal complying with the LVDS standard (TIA/EIA-644). The differential output signal operates with a signal level of 360 mV (nominally) at a common-mode voltage of 1.2 V. This low differential output voltage results in low electromagnetic interference (EMI). The differential nature of the output provides immunity to common-mode coupled signals that the driven signal may experience.

The DS90LV027AH is primarily used in point-to-point configurations, as seen in Figure 20. This configuration provides a clean signaling environment for the fast edge rates of the DS90LV027AH and other LVDS drivers. The DS90LV027AH is connected through a balanced media which may be a standard twisted-pair cable, a parallel pair cable, or simply PCB traces to a LVDS receiver. Typically, the characteristic differential impedance of the media is in the range of 100 Ω. The DS90LV027AH device is intended to drive a 100-Ω transmission line. The 100-Ω termination resistor is selected to match the media and is placed as close to the LVDS receiver input pins as possible.