JAJSGU9B September   2005  – January 2019 DS90LV028AH

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      接続図
      2.      機能図
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Termination
      2. 8.3.2 Threshold
      3. 8.3.3 Fail-Safe Feature
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Receiver Bypass Capacitance
        2. 9.2.2.2 Interconnecting Media
        3. 9.2.2.3 PCB Transmission Lines
        4. 9.2.2.4 Input Fail-Safe Biasing
        5. 9.2.2.5 Probing LVDS Transmission Lines on PCB
        6. 9.2.2.6 Cables and Connectors, General Comments
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Microstrip vs. Stripline Topologies
      2. 11.1.2 Dielectric Type and Board Construction
      3. 11.1.3 Recommended Stack Layout
      4. 11.1.4 Separation Between Traces
      5. 11.1.5 Crosstalk and Ground Bounce Minimization
      6. 11.1.6 Decoupling
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 関連資料
    2. 12.2 ドキュメントの更新通知を受け取る方法
    3. 12.3 コミュニティ・リソース
    4. 12.4 商標
    5. 12.5 静電気放電に関する注意事項
    6. 12.6 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.6 Switching Characteristics

VCC = +3.3 V ± 10%, TA = −40°C to +125°C(1)(2)
PARAMETER MIN TYP MAX UNIT
tPHLD Differential Propagation Delay High to Low CL = 15 pF
VID = 200 mV
(Figure 14 and Figure 15) 		1 1.6 2.5 ns
tPLHD Differential Propagation Delay Low to High 1 1.7 2.5 ns
tSKD1 Differential Pulse Skew |tPHLD − tPLHD|(3) 0 50 650 ps
tSKD2 Differential Channel-to-Channel Skew-same device(4) 0 0.1 0.5 ns
tSKD3 Differential Part to Part Skew(5) 0 1 ns
tSKD4 Differential Part to Part Skew(6) 0 1.5 ns
tTLH Rise Time 325 800 ps
tTHL Fall Time 225 800 ps
fMAX Maximum Operating Frequency(7) 200 250 MHz
(1) CL includes probe and jig capacitance.
(2) Generator waveform for all tests unless otherwise specified: f = 1 MHz, ZO = 50 Ω, tr and tf (0% to 100%) ≤ 3 ns for RIN.
(3) tSKD1 is the magnitude difference in differential propagation delay time between the positive-going-edge and the negative-going-edge of the same channel.
(4) tSKD2 is the differential channel-to-channel skew of any event on the same device. This specification applies to devices having multiple receivers within the integrated circuit.
(5) tSKD3, part to part skew, is the differential channel-to-channel skew of any event between devices. This specification applies to devices at the same VCC and within 5°C of each other within the operating temperature range.
(6) tSKD4, part to part skew, is the differential channel-to-channel skew of any event between devices. This specification applies to devices over the recommended operating temperature and voltage ranges, and across process distribution. tSKD4 is defined as |Max − Min| differential propagation delay.
(7) fMAX generator input conditions: tr = tf < 1 ns (0% to 100%), 50% duty cycle, differential (1.05 V to 1.35 V peak-to-peak). Output criteria: 60%/40% duty cycle, VOL (max 0.4 V), VOH (min 2.7 V), load = 15 pF (stray plus probes).