JAJSGU9B September   2005  – January 2019 DS90LV028AH

PRODUCTION DATA.  

  1. 特長
  2. アプリケーション
  3. 概要
    1.     Device Images
      1.      接続図
      2.      機能図
  4. 改訂履歴
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. Parameter Measurement Information
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Termination
      2. 8.3.2 Threshold
      3. 8.3.3 Fail-Safe Feature
    4. 8.4 Device Functional Modes
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Receiver Bypass Capacitance
        2. 9.2.2.2 Interconnecting Media
        3. 9.2.2.3 PCB Transmission Lines
        4. 9.2.2.4 Input Fail-Safe Biasing
        5. 9.2.2.5 Probing LVDS Transmission Lines on PCB
        6. 9.2.2.6 Cables and Connectors, General Comments
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Microstrip vs. Stripline Topologies
      2. 11.1.2 Dielectric Type and Board Construction
      3. 11.1.3 Recommended Stack Layout
      4. 11.1.4 Separation Between Traces
      5. 11.1.5 Crosstalk and Ground Bounce Minimization
      6. 11.1.6 Decoupling
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 関連資料
    2. 12.2 ドキュメントの更新通知を受け取る方法
    3. 12.3 コミュニティ・リソース
    4. 12.4 商標
    5. 12.5 静電気放電に関する注意事項
    6. 12.6 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Overview

The DS90LV028AH is a dual-channel, low-voltage differential signaling (LVDS) line receiver. It operates from a single power supply that is nominally 3.3 V, but the supply can be as low as 3 V and as high as 3.6 V. The input to the DS90LV028AH is a differential signal that complies with the LVDS Standard (TIA/EIA-644), and the output is a 3.3-V LVCMOS/LVTTL signal. The differential input signal operates with a signal level of 350 mV (nominally) at a common-mode voltage of 1.2 V. The differential nature of the inputs provides immunity to common-mode coupled signals that the driven signal may experience. A termination resistor of 100 Ω should be used with DS90LV028AH.

LVDS receivers are intended to be used primarily in point-to-point configurations. This type of configuration provides a clean signaling environment for the fast edge rates of the drivers. The receiver is connected to the driver through a balanced media that may be a standard twisted-pair cable, a parallel pair cable, or simply PCB traces. Typically, the characteristic impedance of the media is in the range of 100 Ω. The integrated termination resistor converts the driver output (current mode) into a voltage without the need for external termination and is detected by the receiver. Other configurations are possible such as a multi-receiver configuration, but the effects of a mid-stream connector(s), cable stub(s), and other impedance discontinuities as well as ground shifting, noise margin limits, and total termination loading must be taken into account.