JAJSOA9A March   2022  – October 2022 INA851

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 説明
  4. 4 Revision History
  5. 5 Related Products
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Adjustable Gain Setting
        1. 8.3.1.1 Gain Drift
      2. 8.3.2 Offset Voltage
      3. 8.3.3 Input Common-Mode Range
      4. 8.3.4 Input Protection
      5. 8.3.5 Output Clamping
      6. 8.3.6 Low Noise
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Output Common-Mode Pin
      2. 9.1.2 Output-Stage Gain Selection and Noise-Gain Shaping
      3. 9.1.3 Input Bias Current Return Path
      4. 9.1.4 Thermal Effects due to Power Dissipation
    2. 9.2 Typical Applications
      1. 9.2.1 Three-Pin Programmable Logic Controller (PLC)
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 アプリケーション曲線
      2. 9.2.2 20-Bit, 1-MSPS ADS8900B Driver Circuit With FDA Noise Filter
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Application Curves
      3. 9.2.3 24-Bit, 200 kSPS, Delta-Sigma ADS127L11 ADC Driver Circuit With FDA Noise Filter
        1. 9.2.3.1 Design Requirements
        2. 9.2.3.2 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Development Support
        1. 10.1.1.1 PSpice® for TI
        2. 10.1.1.2 TINA-TI™シミュレーション・ソフトウェア (無償ダウンロード)
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 サポート・リソース
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.5 Electrical Characteristics

at TA = 25°C, VS = ±15 V, VICM = VOCM = midsupply, VCLAMP+ = VS+, VCLAMP– = VS–, G = GIN = GOUT = 1 V/V, and RL = 10 kΩ (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INPUT
VOSI Input stage offset voltage(1) ±10 ±35 µV
TA = –40°C to +125°C(4) ±65
Input stage offset voltage drift(2) TA = –40°C to +125°C(4) ±0.1 ±0.3 µV/°C
VOSO Output stage offset voltage(1) G = 0.2 ±150 ±1150 µV
G = 1 ±150 ±650
Output stage offset voltage drift(2) TA = –40°C to +125°C(4) G = 0.2 ±5 ±15 µV/°C
G = 1 ±5 ±15
PSRR Power-supply rejection ratio ±4 V ≤ VS ≤ ±18 V, RTI G = 0.2 100 120 dB
G = 1 110 126
GIN = 10 120 140
GIN = 100 126 140
GIN = 1000 130 140
zid Differential impedance 1 || 100 pF || GΩ
zic Common-mode impedance 7 || 100 pF || GΩ
VIN Input voltage(5)(6) See also INA851 Calculator Tool (VS–) + 2.5 (VS+) – 2.5 V
Protected input voltage(9) (VS–) – 40 (VS+) + 40 V
Input current in overvoltage mode(9) (VS–) – 40 V ≤ VIN ≤ (VS+) + 40 V(3) 16 mA
CMRR Common-mode rejection ratio At dc to 60 Hz, RTI,
VCM = (VS–) + 2.5 V to (VS+) – 2.5 V		 G = 0.2 76 90 dB
G = 1 86 96
GIN = 10 106 116
GIN = 100 120 132
GIN = 1000 120 134
BIAS CURRENT
IB Input bias current 5 15 nA
TA = –40°C to +125°C(5) 18
Input bias current drift TA = –40°C to +125°C 25 pA/°C
IOS Input offset current 0.5 5.5 nA
TA = –40°C to +125°C(5) 6
Input offset current drift TA = –40°C to +125°C 5 pA/°C
NOISE VOLTAGE
eNI Input stage voltage noise density f = 1 kHz, G = 1000 3.2 nV/√Hz
Input stage voltage noise fB = 0.1 Hz to 10 Hz, G = 1000 0.1 µVPP
eNO Output stage voltage noise density(7) f = 1 kHz G = 0.2 83 nV/√Hz
G = 1 52
G = 1;
GIN = 5, GOUT = 0.2 		 12
Output stage voltage noise(7) fB = 0.1 Hz to 10 Hz G = 0.2 5.0 µVPP
G = 1 2.8 µVPP
Current noise density f = 1 kHz, GIN = 1000 0.8 pA/√Hz
In Current noise fB = 0.1 Hz to 10 Hz, G = 100 37 pAPP
GAIN
Gain equation G = GIN × GOUT  (1 + (6 kΩ / RG)) × (0.2 or 1) V/V
G Gain GOUT = 0.2 0.2 2000 V/V
GOUT = 1 1 10000
GE Gain error G = 0.2, VO = ±2 V ±0.1 %
G = 1, VO = ±10 V ±0.02
GIN ≥ 10, VO = ±10 V ±0.2
Gain drift(6) TA = –40°C to +125°C(4) G = 0.2 ±5 ppm/°C
G = 1 ±5
GIN > 1 ±35
Gain nonlinearity G = 0.2, VO = –2 V to +2 V ±5 ppm
G = 1, VO = –10 V to +10 V ±5
OUTPUT
VO Output voltage swing IOUT = 10 mA,
TA = –40°C to +125°C		 No output clamping
(VCLAMP+ = VS+,
VCLAMP– = VS–)		 (VS–) + 1.4 (VS+) – 1.4 V
Output clamping enabled
(VCLAMP+ = VS+ –1.5 V,
VCLAMP– = VS–+1.5 V)		 (VCLAMP–) – 0.1 (VCLAMP+) + 0.1
CL Load capacitance  Stable operation for differential load 100 pF
ZO Closed-loop output impedance f = 1 MHz 0.9 Ω
ISC Short-circuit current TA = –40°C to 125°C, continuous to VS / 2 ±37 mA
FREQUENCY RESPONSE
BW Bandwidth, –3 dB G = 0.2 22 MHz
G = 1, GIN = 5, GOUT = 0.2 22
G = 1 15
GIN = 10 11
GIN = 100 5
GIN = 1000 0.8
SR Slew rate G = 1, VO = ±10 V 37 V/µs
tS Settling time 0.01% G = 0.2, VSTEP = 2 V 0.24 µs
G = 1, VSTEP = 10 V 0.24
GIN = 10, 100, VSTEP = 10 V 0.5
GIN = 1000, VSTEP = 10 V 1.7
0.001% G = 0.2, VSTEP = 2 V 0.55 µs
G = 1, VSTEP = 10 V 0.55
GIN = 10,100, VSTEP = 10 V 2.1
GIN = 1000, VSTEP = 10 V 2.5
THD+N Total harmonic distortion plus noise Differential input, f = 10 kHz G = 0.2, VO = 2 VPP –109 dB
G = 1, VO = 10 VPP –110
HD2 Second-order harmonic distortion Differential input, f = 10 kHz G = 0.2, VO = 2 VPP –131 dB
G = 1, VO = 10 VPP –128
HD3 Third-order harmonic distortion Differential input, f = 10 kHz G = 0.2, VO = 2 VPP –119 dB
G = 1, VO = 10 VPP –121
OUTPUT COMMON-MODE VOLTAGE (VOCM) CONTROL
VOCM Input voltage TA = –40°C to +125°C No output clamping (VS–) + 2.5 (VS+) – 2.5 V
Output clamp enabled (VCLAMP–) + 1 (VCLAMP+) – 1
Small-signal bandwidth from VOCM pin VOCM = 100 mVPP 30 MHz
Large-signal bandwidth from VOCM pin VOCM = 0.5-V step 47 MHz
Slew rate from VOCM pin VOCM = 0.5-V step 37 V/µs
DC output balance VOCM fixed midsupply (VO = ±1 V) 70 dB
Input impedance VVOCM pin 250 || 1 kΩ || pF
VOCM offset from mid-supply VOCM pin floating ±2 ±6 mV
VOCM common-mode offset voltage VOCM = VICM, VO = 0 V ±2 ±6 mV
TA = –40°C to +125°C ±10
VOCM common-mode offset voltage drift VOCM = VICM, VO = 0 V, TA = –40°C to +125°C ±20 ±60 µV/°C
OUTPUT CLAMPING
VCLAMP+ Positive clamp voltage(11) TA = –40°C to +125°C No output clamping VS+ V
Output clamp enabled VS+ – 1.5
VCLAMP– Negative clamp voltage(11) TA = –40°C to +125°C No output clamping VS– V
Output clamp enabled VS– + 1.5
ΔVCLAMP Clamp voltage(11) ΔVCLAMP = (VCLAMP+) – (VCLAMP–) 3 V
Power-supply rejection ratio from VCLAMP to VO(4) 120 dB
Fail-safe current VCLAMP+ VS+ = VS– = 0 V, VCLAMP+ = 10 V 2 mA
ICLAMP+ Positive clamp current VCLAMP+ ≤ VS+ – 1.5 V –80 –60 µA
ICLAMP– Negative clamp current VCLAMP– ≥ VS– + 1.5 V 60 80 µA
POWER SUPPLY
IQ Quiescent current VIN = 0 V 6 7 mA
TA = –40°C to +125°C 9
(1) Offset voltages are uncorrelated. Total offset voltage, referred-to-input (RTI): VOS = √[VOSI2 + (VOSO(Gout1 or Gout0.2) / GIN)2]. See more details on Offset Voltage section.
(2) Offset drifts are uncorrelated. Offset drift, referred-to-input (RTI): ΔVOS(RTI) = √[ΔVOSI2 + (ΔVOSO / GIN)2].
(3) Specified by design.
(4) Specified by characterization.
(5) Input voltage range of the instrumentation amplifier input stage. The valid input range depends on the common-mode voltage, differential voltage, gain, and VOCM. See also the Input Common-Mode Range section.
(6) The values specified for G > 1 do not include the effects of the external gain-setting resistor, RG.
(7) eNO refers to output stage noise referred to the input of the FDA. See also the Noise Equivalent Model section.
(8) See also the Input Protection section.
(9) See also the Typical Characteristics section.
(10) See also the Output Clamping section.