SNOSC68C April   2012  – September 2015 LM3533

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 I2C Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Control Bank Mapping
        1. 7.3.1.1 High-Voltage Control Banks (A/B)
        2. 7.3.1.2 Low-Voltage Control Banks (C, D, E, And F)
      2. 7.3.2 Pattern Generator
      3. 7.3.3 Ambient Light Sensor Interface
      4. 7.3.4 PWM Input
      5. 7.3.5 HWEN Input
      6. 7.3.6 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1  High-Voltage Boost Converter
        1. 7.4.1.1 High-Voltage Current Sinks (HVLED1 And HVLED2)
        2. 7.4.1.2 High-Voltage Current String Biasing
        3. 7.4.1.3 Boost Switching-Frequency Select
      2. 7.4.2  Integrated Charge Pump
        1. 7.4.2.1 Charge Pump Disabled
        2. 7.4.2.2 Automatic Gain
        3. 7.4.2.3 Automatic Gain (Flying Capacitor Detection)
        4. 7.4.2.4 1× Gain
        5. 7.4.2.5 2× Gain
        6. 7.4.2.6 Low-Voltage Current Sinks (LVLED1 to LVLED5)
        7. 7.4.2.7 Low-Voltage LED Biasing
      3. 7.4.3  LED Current Mapping Modes
        1. 7.4.3.1 Exponential Mapping
        2. 7.4.3.2 Linear Mapping
      4. 7.4.4  LED Current Ramping
        1. 7.4.4.1 Start-Up/Shutdown Ramp
        2. 7.4.4.2 Run-Time Ramp
      5. 7.4.5  Brightness Register Current Control
      6. 7.4.6  PWM Control
        1. 7.4.6.1 PWM Input Frequency Range
        2. 7.4.6.2 PWM Input Polarity
      7. 7.4.7  ALS Current Control
        1. 7.4.7.1 ALS Brightness Zones (Zone Boundaries)
        2. 7.4.7.2 Zone Boundary Hysteresis
        3. 7.4.7.3 Zone Target Registers (ALSM1, ALSM2, ALSM3)
        4. 7.4.7.4 PWM Input in ALS Mode
      8. 7.4.8  ALS Functional Blocks
        1. 7.4.8.1  ALS Input
        2. 7.4.8.2  Analog Output Ambient Light Sensors (ALS Gain Setting Resistors)
        3. 7.4.8.3  PWM Output Ambient Light Sensors (Internal Filtering)
        4. 7.4.8.4  Internal 8-Bit ADC
        5. 7.4.8.5  ALS Averager
        6. 7.4.8.6  Initializing the ALS
        7. 7.4.8.7  ALS Algorithms
        8. 7.4.8.8  ALS Rules
        9. 7.4.8.9  Direct ALS Control
        10. 7.4.8.10 Up-Only Control
        11. 7.4.8.11 Down-Delay Control
      9. 7.4.9  Pattern Generator
        1. 7.4.9.1 Delay Time
        2. 7.4.9.2 Rise Time
        3. 7.4.9.3 Fall Time
        4. 7.4.9.4 High Period
        5. 7.4.9.5 Low Period
        6. 7.4.9.6 Low-Level Brightness
        7. 7.4.9.7 High-Level Brightness
        8. 7.4.9.8 ALS Controlled Pattern Current
        9. 7.4.9.9 Interrupt Output Mode
      10. 7.4.10 Fault Flags/Protection Features
        1. 7.4.10.1 Open LED String (HVLED)
        2. 7.4.10.2 Shorted LED String (HVLED)
        3. 7.4.10.3 Open LED (LVLED)
        4. 7.4.10.4 Shorted LED (LVLED)
        5. 7.4.10.5 Overvoltage Protection (Inductive Boost)
        6. 7.4.10.6 Current Limit (Inductive Boost)
        7. 7.4.10.7 Current Limit (Charge Pump)
    5. 7.5 Programming
      1. 7.5.1 I2C-Compatible Interface
        1. 7.5.1.1 Start and Stop Conditions
        2. 7.5.1.2 I2C-Compatible Address
        3. 7.5.1.3 Transferring Data
    6. 7.6 Register Maps
      1. 7.6.1 LM3533 Register Descriptions
        1. 7.6.1.1 Pattern Generator Registers
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Boost Converter Maximum Output Power (Boost)
        2. 8.2.2.2 Peak Current Limited
        3. 8.2.2.3 Output Voltage Limited
        4. 8.2.2.4 Maximum Output Power (Charge Pump)
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Boost
        1. 10.1.1.1 Boost Output Capacitor Selection and Placement
        2. 10.1.1.2 Schottky Diode Placement
        3. 10.1.1.3 Inductor Placement
        4. 10.1.1.4 Boost Input Capacitor Selection and Placement
      2. 10.1.2 Charge Pump
        1. 10.1.2.1 Flying Capacitor (CP)
        2. 10.1.2.2 Output Capacitor (CPOUT)
        3. 10.1.2.3 Charge Pump Input Capacitor Placement
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Related Documentation
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

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発注情報

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)(2)(3)
MIN MAX UNIT
VIN to GND −0.3 6 V
VSW, VOVP, VHVLED1, VHVLED2 to GND −0.3 45 V
VSCL, VSDA, VALS, VPWM to GND −0.3 6 V
VINT, VHWEN, VCPOUT to GND −0.3 6 V
VLVLED1- VLVLED5, to GND −0.3 6 V
Continuous power dissipation Internally limited
Junction temperature, TJ-MAX 150 °C
Maximum lead temperature (soldering) See(4)
Storage temperature, Tstg –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to the potential at the GND pin.
(3) If Military/Aerospace specified devices are required, contact the TI Sales Office/Distributors for availability and specifications.
(4) For detailed soldering specifications and information, refer to Texas Instruments Application Note 1112: DSBGA Wafer Level Chip Scale Package (SNVA009) available at www.ti.com.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)(1)
MIN NOM MAX UNIT
VIN to GND 2.7 5.5 V
VSW, VOVP, VHVLED1, VVHLED2 to GND 0 40 V
VLVLED1- VLVLED5 to GND 0 6 V
Junction temperature (TJ)(2)(3) −40 125 °C
(1) All voltages are with respect to the potential at the GND pin.
(2) Internal thermal shutdown circuitry protects the device from permanent damage. Thermal shutdown engages at TJ = 140°C (typical) and disengages at TJ= 125°C (typical).
(3) In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may have to be derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-OP = 125°C), the maximum power dissipation of the device in the application (PD-MAX), and the junction-to ambient thermal resistance of the part/package in the application (RθJA), as given by the equation: TA-MAX = TJ-MAX-OP – (RθJA × PD-MAX).

6.4 Thermal Information

THERMAL METRIC(1) LM3533 UNIT
YFQ (DSBGA)
20 PINS
RθJA Junction-to-ambient thermal resistance(2) 55.3 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.
(2) Junction-to-ambient thermal resistance (RJθA) is taken from a thermal modeling result, performed under the conditions and guidelines set forth in the JEDEC standard JESD51-7. The test board is a 4-layer FR-4 board measuring 102 mm × 76 mm × 1.6 mm with a 2 × 1 array of thermal vias. The ground plane on the board is 50 mm × 50 mm. Thickness of copper layers are 36 µm/18 µm/18 µm/36 µm (1.5 oz/1 oz/1 oz/1.5 oz). Ambient temperature in simulation is 22°C in still air. Power dissipation is 1 W. The value of RθJA of this product in the DSBGA package could fall in a range as wide as 60°C/W to 110°C/W (if not wider), depending on PCB material, layout, and environmental conditions. In applications where high maximum power dissipation exists special care must be paid to thermal dissipation issues.

6.5 Electrical Characteristics

Unless otherwise specified VIN = 3.6 V; typical limits are for TA = 25°C and minimum and maximum limits apply over the full operating ambient temperature range (−40°C ≤ TA ≤ +85°C).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ISHDN Shutdown current 2.7 V ≤ VIN ≤ 5.5 V, HWEN = GND 1 5 µA
ILED_MIN Minimum LED current Full-scale current = 20.2 mA
Exponential mapping 		9.5 µA
TSD Thermal shutdown 140 °C
Hysteresis 15
BOOST CONVERTER
IHVLED(1/2) Output current regulation (HVLED1 or HVLED2) 2.7 V ≤ VIN ≤ 5.5 V
full-scale current = 20.2mA, brightness code = 0xFF		 17 20.2 23 mA
IMATCH_HV HVLED1 to HVLED2 matching (1) 2.7 V ≤ VIN ≤ 5.5 V Both current sinks are assigned to Control Bank A –2% 1% 2%
VREG_CS Regulated current sink headroom voltage 400 mV
VHR_HV Minimum current sink headroom voltage for HVLED current sinks ILED = 95% of nominal
full-scale current = 20.2 mA 		190 250 mV
RDSON NMOS switch on resistance ISW = 500 mA 0.3 Ω
ICL_BOOST NMOS switch current limit VIN = 3.6 V 880 1000 1120 mA
VOVP Output overvoltage protection ON threshold, 2.7 V ≤ VIN ≤ 5.5 V
OVP select bits = 11		 39 40 41 V
Hysteresis 1
ƒSW Switching frequency 2.7 V ≤ VIN ≤ 5.5 V Boost frequency select bit = 0 450 500 550 kHz
Boost frequency select bit = 1 900 1000 1100
DMAX Maximum duty cycle 94%
CHARGE PUMP
ILVLED(1/2/3/4/5) Output current regulation (low-voltage current sinks) 2.7 V ≤ VIN ≤ 5.5 V, full-scale current = 20.2 mA
brightness code = 0xFF		 17 20.2 23 mA
IMATCH_LV LVLED current sink matching (2) 2.7 V ≤ VIN ≤ 5.5 V –2% 1% 2%
VHR_LV Minimum current sink headroom voltage for LVLED current sinks ILED = 95% of nominal, full-scale current = 20.2 mA 80 110 mV
VGTH Threshold for gain transition VLVLED falling 110 mV
ICL_PUMP Charge-pump current limit 3 V ≤ VIN ≤ 5.5 V, output referred 1× gain 180 350 mA
2× gain 240
ROUT Charge-pump output resistance 1× gain 1.1 Ω
HWEN INPUT
VHWEN Logic thresholds Logic low 0 0.4 V
Logic high 1.2 VIN
PWM INPUT
VPWM_L Input logic low 2.7 V ≤ VIN ≤ 5.5 V 0 400 mV
VPWM_H Input logic high 2.7 V ≤ VIN ≤ 5.5 V 1.25 VIN V
INT OUTPUT
VLOW Output Logic Low (INT Mode) 2.7 V ≤ VIN ≤ 5.5 V 400 mV
I2C-COMPATIBLE VOLTAGE SPECIFICATIONS (SCL, SDA)
VIL Input logic low 2.7 V ≤ VIN ≤ 5.5 V 0 400 mV
VIH Input logic high 2.7 V ≤ VIN ≤ 5.5 V 1.25 VIN V
VOL Output logic low (SDA) ILOAD = 3mA 400 mV
AMBIENT LIGHT SENSOR (ALS)
RALS ALS internal pulldown resistor in analog sensor input mode R_ALS Select Register = 0x0F
2.7 V ≤ VIN ≤ 5.5 V		 12.36 13.33 13.94 kΩ
VALS_REF Ambient Light Sensor Reference Voltage 2.7 V ≤ VIN ≤ 5.5 V 1.9 2 2.1 V
VALS_MIN Minimum Threshold for ALS Input Voltage Sensing Analog sensor mode
2.7 V ≤ VIN ≤ 5.5 V, Code 0 to 1 transition point		 3 10 15 mV
tCONV Conversion Time 140 µs
LSB ADC Resolution 2.7 V ≤ VIN ≤ 5.5 V 7.8 mV
(1) LED current sink matching between HVLED1 and HVLED2 is given by taking the difference between either (IHVLED1 or IHVLED2) and the average current between the two, and dividing by the average current between the two. This simplifies to (IHVLED1 (or IHVLED2) – IHVLED(AVE))/(IHVLED(AVE)) × 100. In this test, both HVLED1 and HVLED2 are assigned to Bank A.
(2) LED current sink matching in the low-voltage current sinks (LVLED1 through LVLED5) is given as the maximum matching value between any two current sinks, where the matching between any two low voltage current sinks (X and Y) is given as (ILVLEDX (or ILVLEDY) – IAVE(X-Y))/(IAVE(X-Y)) × 100. In this test all LVLED current sinks are assigned to Bank C.

6.6 I2C Timing Requirements

MIN NOM MAX UNIT
t1 SCL (Clock Period) 2.5 µs
t2 Data In Setup Time to SCL High 100 ns
t3 Data Out Stable After SCL Low 0 ns
t4 SDA Low Setup Time to SCL Low (Start) 100 ns
t5 SDA High Hold Time After SCL High (Stop) 100 ns

6.7 Typical Characteristics

VIN = 3.6 V, LEDs are WLEDs part number SML-312WBCW(A), typical application circuit with L = TDK (VLF302512, 4.7 µH, 10 µH, 22 µH where specified), Schottky = On-Semi (NSR0240V2T1G), TA = 25°C, unless otherwise specified. Efficiency is given as VOUT × (IHVLED1 + IHVLED2)/(VIN × IIN); matching curves are given as (ΔILED_MAX/ILED_AVE).
LM3533 30135766.gif
ILED = 20 mA
Figure 1. HVLED Matching vs VIN, Temp
LM3533 30135775.gif
VIN = 3.6 V
Figure 3. HVLED Current vs Code (Exponential Mode)
LM3533 30135777.gif
VIN = 3.6 V
Figure 5. HVLED Matching vs Code (Linear Mode)
LM3533 30135765.gif
Figure 7. LVLED Current vs Current Sink Headroom Voltage
LM3533 30135763.gif
Figure 9. ALS Resistance vs Code (Temp)
LM3533 30135768.gif
Figure 11. Shutdown Current vs VIN
LM3533 30135769.gif
50% Duty Cycle ILED Full_scale = 20.2 mA
Figure 13. Led Current Ripple vs FPWM
LM3533 30135772.gif
1x Gain
Figure 15. IN to CPOUT Resistance vs VIN
LM3533 30135780.gif
1× Gain
Figure 17. Charge Pump Short Circuit Current Limit vs VIN
LM3533 30135781.gif
VIN = 3.6 V 20 mA/String 2×8 LEDs
Figure 19. Start-Up Response
LM3533 30135783.gif
2×8 LEDs 20.2 mA/String
Figure 21. Line Step Response (see Typical Application Circuit )
LM3533 30135767.gif
ILED = 20 mA
Figure 2. LVLED Matching vs VIN, Temp
LM3533 30135776.gif
VIN = 3.6 V
Figure 4. HVLED Matching vs Code (Exponential Mode)
LM3533 30135764.gif
Figure 6. HVLED Current vs Current Sink Headroom Voltage
LM3533 30135762.gif
VALS = 2 V
Figure 8. ALS Input Current vs Code
LM3533 30135761.gif
(Code 0x50)
Figure 10. ALS Resistance vs VIN
LM3533 30135770.gif
Figure 12. Closed Loop Current Limit vs VIN
LM3533 30135771.gif
Figure 14. NMOS On Resistance vs VIN
LM3533 30135779.gif
2× Gain
Figure 16. Charge Pump Short Circuit Current Limit vs VIN
LM3533 30135778.gif
Figure 18. Idle State Supply Current (Pattern Generator Enabled On LVLED1, LVLED2, LVLED3)
LM3533 30135782.gif
D = 30% To 90% ƒPWM = 10 kHz
ILED_FULL SCALE = 20.2 mA
Figure 20. Response To Step Change in PWM Input Duty Cycle