JAJSG75A September   2018  – March 2019 LM5164-Q1

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      代表的なアプリケーション
      2.      代表的なアプリケーションの効率、VOUT = 12V時
  4. 4 改訂履歴
  5. 5 概要 (続き)
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Control Architecture
      2. 8.3.2  Internal VCC Regulator and Bootstrap Capacitor
      3. 8.3.3  Regulation Comparator
      4. 8.3.4  Internal Soft Start
      5. 8.3.5  ON-Time Generator
      6. 8.3.6  Current Limit
      7. 8.3.7  N-Channel Buck Switch and Driver
      8. 8.3.8  Synchronous Rectifier
      9. 8.3.9  Enable/Undervoltage Lockout (EN/UVLO)
      10. 8.3.10 Power Good (PGOOD)
      11. 8.3.11 Thermal Protection
    4. 8.4 Device Functional Modes
      1. 8.4.1 Shutdown Mode
      2. 8.4.2 Active Mode
      3. 8.4.3 Sleep Mode
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Custom Design With WEBENCH® Tools
        2. 9.2.2.2 Switching Frequency (RRON)
        3. 9.2.2.3 Buck Inductor (LO)
        4. 9.2.2.4 Output Capacitor (COUT)
        5. 9.2.2.5 Input Capacitor (CIN)
        6. 9.2.2.6 Type 3 Ripple Network
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Compact PCB Layout for EMI Reduction
      2. 11.1.2 Feedback Resistors
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 デバイス・サポート
      1. 12.1.1 デベロッパー・ネットワークの製品に関する免責事項
      2. 12.1.2 開発サポート
        1. 12.1.2.1 WEBENCH® ツールによるカスタム設計
    2. 12.2 関連資料
    3. 12.3 ドキュメントの更新通知を受け取る方法
    4. 12.4 コミュニティ・リソース
    5. 12.5 商標
    6. 12.6 静電気放電に関する注意事項
    7. 12.7 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

11.1.1 Compact PCB Layout for EMI Reduction

Radiated EMI generated by high di/dt components relates to pulsing currents in switching converters. The larger area covered by the path of a pulsing current, the more electromagnetic emission is generated. The key to minimizing radiated EMI is to identify the pulsing current path and minimize the area of that path.

The critical switching loop of the buck converter power stage in terms of EMI is denoted in Figure 27. The topological architecture of a buck converter means that a particularly high di/dt current path exists in the loop comprising the input capacitor and the integrated MOSFETs of the LM5164-Q1, and it becomes mandatory to reduce the parasitic inductance of this loop by minimizing the effective loop area.

LM5164-Q1 Power_loops_nvsb51.gifFigure 27. DC/DC Buck Converter With Power Stage Circuit Switching Loop

The input capacitor provides the primary path for the high di/dt components of the high-side MOSFET's current. Placing a ceramic capacitor as close as possible to the VIN and GND pins is the key to EMI reduction. Keep the trace connecting SW to the inductor as short as possible and just wide enough to carry the load current without excessive heating. Use short, thick traces or copper pours (shapes) for current conduction path to minimize parasitic resistance. Place the output capacitor close to the VOUT side of the inductor, and connect the capacitor's return terminal to the GND pin and exposed PAD of the LM5164-Q1.