JAJSLZ9A December   2021  – November 2022 LMH5485-SEP

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics: Vs+ – Vs- = 5 V
    6. 7.6 Electrical Characteristics: Vs+ – Vs- = 3 V
    7. 7.7 Typical Characteristics: 5 V Single Supply
    8. 7.8 Typical Characteristics: 3 V Single Supply
    9. 7.9 Typical Characteristics: 3 V to 5 V Supply Range
  8. 8 Parameter Measurement Information
    1. 8.1 Example Characterization Circuits
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Differential I/O
      2. 9.3.2 Power-Down Control Pin (PD)
        1. 9.3.2.1 Operating the Power Shutdown Feature
      3. 9.3.3 Input Overdrive Operation
    4. 9.4 Device Functional Modes
      1. 9.4.1 Operation from Single-Ended Sources to Differential Outputs
        1. 9.4.1.1 AC-Coupled Signal Path Considerations for Single-Ended Input to Differential Output Conversion
        2. 9.4.1.2 DC-Coupled Input Signal Path Considerations for Single-Ended to Differential Conversion
      2. 9.4.2 Differential-Input to Differential-Output Operation
        1. 9.4.2.1 AC-Coupled, Differential-Input to Differential-Output Design Issues
        2. 9.4.2.2 DC-Coupled, Differential-Input to Differential-Output Design Issues
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Applications
      1. 10.2.1 Designing Attenuators
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
        3. 10.2.1.3 Application Curve
      2. 10.2.2 Interfacing to High-Performance ADCs
        1. 10.2.2.1 Design Requirements
        2. 10.2.2.2 Detailed Design Procedure
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 Receiving Notification of Documentation Updates
    3. 13.3 サポート・リソース
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

パッケージ・オプション

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メカニカル・データ（パッケージ｜ピン）
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発注情報

9.3.2.1 Operating the Power Shutdown Feature

When the PD pin is asserted high, close to the positive supply, the device will be in normal active mode of operation. To disable the device for reduced power consumption, PD pin must be asserted low, close to the negative supply. Figure 7-22 shows the PD pin voltage and the corresponding quiescent current drawn. For applications that require the device to only be powered on when the supplies are present, tie the PD pin to the positive supply voltage.

The disable operation is referenced from the negative supply (normally, ground). For split-supply operation, with the negative supply below ground, a disable control voltage below ground is required to turn the LMH5485-SEP off when the negative supply exceeds –0.7 V.

For single-supply operation, a minimum of 1.7 V above the negative supply (ground, in this case) is required to assure operation. This minimum logic-high level allows for direct operation from 1.8 V supply logic.