JAJSLZ9A December   2021  – November 2022 LMH5485-SEP

PRODUCTION DATA  

  1. 特長
  2. アプリケーション
  3. 概要
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics: Vs+ – Vs- = 5 V
    6. 7.6 Electrical Characteristics: Vs+ – Vs- = 3 V
    7. 7.7 Typical Characteristics: 5 V Single Supply
    8. 7.8 Typical Characteristics: 3 V Single Supply
    9. 7.9 Typical Characteristics: 3 V to 5 V Supply Range
  8. Parameter Measurement Information
    1. 8.1 Example Characterization Circuits
  9. Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Differential I/O
      2. 9.3.2 Power-Down Control Pin (PD)
        1. 9.3.2.1 Operating the Power Shutdown Feature
      3. 9.3.3 Input Overdrive Operation
    4. 9.4 Device Functional Modes
      1. 9.4.1 Operation from Single-Ended Sources to Differential Outputs
        1. 9.4.1.1 AC-Coupled Signal Path Considerations for Single-Ended Input to Differential Output Conversion
        2. 9.4.1.2 DC-Coupled Input Signal Path Considerations for Single-Ended to Differential Conversion
      2. 9.4.2 Differential-Input to Differential-Output Operation
        1. 9.4.2.1 AC-Coupled, Differential-Input to Differential-Output Design Issues
        2. 9.4.2.2 DC-Coupled, Differential-Input to Differential-Output Design Issues
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Applications
      1. 10.2.1 Designing Attenuators
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
        3. 10.2.1.3 Application Curve
      2. 10.2.2 Interfacing to High-Performance ADCs
        1. 10.2.2.1 Design Requirements
        2. 10.2.2.2 Detailed Design Procedure
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 Receiving Notification of Documentation Updates
    3. 13.3 サポート・リソース
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ(パッケージ|ピン)
  • DGK|8
サーマルパッド・メカニカル・データ
発注情報

Detailed Design Procedure

The LMH5485-SEP provides a simple interface to a wide variety of precision SAR, ΔΣ, or higher-speed pipeline ADCs. To deliver the exceptional distortion at the output pins, considerably wider bandwidth than typically required in the signal path to the ADC inputs is provided by the LMH5485-SEP. For instance, the gain of 2 single-ended to differential design example provides approximately a 500 MHz, small-signal bandwidth. Even if the source signal is Nyquist bandlimited, this broad bandwidth can possibly integrate enough LMH5485-SEP noise to degrade the SNR through the ADC if the broadband noise is not bandlimited between the amplifier and ADC. Figure 10-4 shows an example DC-coupled, gain of 2 interface with a controlled, interstage-bandwidth filter.

Designed for a DC-coupled 50 Ω input match, this design starts with a 499 Ω feedback resistor, and provides a gain of 2.35 V/V to the LMH5485-SEP output pins. The third-order interstage, low-pass filter provides a 20 MHz Bessel response with a 0.85 V/V insertion loss to the ADC, providing a net gain of 2 V/V from board edge to the ADC inputs. Although the LMH5485-SEP can absorb overdrives, an external protection element is added using the BAV99 low-capacitance device, shown in Figure 10-4. For DC-coupled testing, pins 1 and 2 of JP1 are jumpered together. When the source is an AC-coupled, 50 Ω source, pins 2 and 3 of JP1 are jumpered to maintain differential balance.