JAJSQ22J september   2011  – may 2023 LMK00301

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Device Comparison
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  9. 8 Parameter Measurement Information
    1. 8.1 Differential Voltage Measurement Terminology
  10. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 VCC and VCCO Power Supplies
    4. 9.4 Device Functional Modes
      1. 9.4.1 Clock Inputs
      2. 9.4.2 Clock Outputs
        1. 9.4.2.1 Reference Output
  11. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
        1. 10.2.1.1 Driving the Clock Inputs
        2. 10.2.1.2 Crystal Interface
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Termination and Use of Clock Drivers
          1. 10.2.2.1.1 Termination for DC Coupled Differential Operation
          2. 10.2.2.1.2 Termination for AC Coupled Differential Operation
          3. 10.2.2.1.3 Termination for Single-Ended Operation
      3. 10.2.3 Application Curves
  12. 11Power Supply Recommendations
    1. 11.1 Power Supply Sequencing
    2. 11.2 Current Consumption and Power Dissipation Calculations
      1. 11.2.1 Power Dissipation Example #1: Separate VCC and VCCO Supplies with Unused Outputs
      2. 11.2.2 Power Dissipation Example #2: Worst-Case Dissipation
    3. 11.3 Power Supply Bypassing
      1. 11.3.1 Power Supply Ripple Rejection
    4. 11.4 Thermal Management
  13. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  14. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 ドキュメントの更新通知を受け取る方法
    3. 13.3 サポート・リソース
    4. 13.4 Trademarks
    5. 13.5 静電気放電に関する注意事項
    6. 13.6 用語集
  15. 14Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報
10.2.2.1.3 Termination for Single-Ended Operation

A balun can be used with either LVDS or LVPECL drivers to convert the balanced, differential signal into an unbalanced, single-ended signal.

It is possible to use an LVPECL driver as one or two separate 800 mV p-p signals. When DC coupling one of the LMK00301 LVPECL driver of a CLKoutX/CLKoutX* pair, be sure to properly terminate the unused driver. When DC coupling on of the LMK00301 LVPECL drivers, the termination should be 50 Ω to Vcco - 2 V as shown in Figure 10-13. The Thevenin equivalent circuit is also a valid termination as shown in Figure 10-14 for Vcco = 3.3 V.

GUID-022A92CA-F2DD-492A-BF90-9BDC25CF5B32-low.gifFigure 10-13 Single-Ended LVPECL Operation, DC Coupling
GUID-BE8A6B3E-1044-4720-9C5D-D4C6FF31A154-low.gifFigure 10-14 Single-Ended LVPECL Operation, DC Coupling, Thevenin Equivalent

When AC coupling an LVPECL driver use a 160 Ω emitter resistor (or 91 Ω for Vcco = 2.5 V) to provide a DC path to ground and ensure a 50 Ω termination with the proper DC bias level for the receiver. The typical DC bias voltage for LVPECL receivers is 2 V. If the companion driver is not used, it should be terminated with either a proper AC or DC termination. This latter example of AC coupling a single-ended LVPECL signal can be used to measure single-ended LVPECL performance using a spectrum analyzer or phase noise analyzer. When using most RF test equipment no DC bias point (0 VDC) is required for safe and proper operation. The internal 50 Ω termination the test equipment correctly terminates the LVPECL driver being measured as shown in Figure 10-15. When using only one LVPECL driver of a CLKoutX/CLKoutX* pair, be sure to properly terminated the unused driver.

GUID-B24F019F-5519-4862-9DE8-32127D5008D7-low.gifFigure 10-15 Single-Ended LVPECL Operation, AC Coupling