JAJSF03K September 2011 – December 2023 LMK03806
PRODUCTION DATA
Table 10-2 shows the default register settings programmed in silicon for the LMK03806 after power on or asserting the reset bit. Capital X and Y represent numeric values.
GROUP | FIELD NAME | DEFAULT VALUE (DECIMAL) | DEFAULT STATE | FIELD DESCRIPTION | REGISTER | BIT LOCATION (MSB:LSB) |
---|---|---|---|---|---|---|
Clock Output Control | CLKout0_1_PD | 1 | PD | Powerdown control for divider, and both output buffers | R0 | 31 |
CLKout2_3_PD | 1 | PD | R1 | |||
CLKout4_5_PD | 1 | PD | R2 | |||
CLKout6_7_PD | 0 | Normal | R3 | |||
CLKout8_9_PD | 0 | Normal | R4 | |||
CLKout10_11_PD | 1 | PD | R5 | |||
RESET | 0 | Not in reset | Performs power on reset for device | R0 | 17 | |
POWERDOWN | 0 | Disabled (device is active) | Device power down control | R1 | 17 | |
CLKout0_1_DIV | 25 | Divide-by-25 | Divide for clock outputs | R0 | 15:5 [11] | |
CLKout2_3_DIV | 25 | Divide-by-25 | R1 | |||
CLKout4_5_DIV | 25 | Divide-by-25 | R2 | |||
CLKout6_7_DIV(1) | 1 | Divide-by-1 | R3 | |||
CLKout8_9_DIV | 25 | Divide-by-25 | R4 | |||
CLKout10_11_DIV | 25 | Divide-by-25 | R5 | |||
CLKout3_TYPE | 0 | Powerdown | Individual clock output format. Select from LVDS/LVPECL/LVCMOS. | R6 | 31:28 [4] | |
CLKout7_TYPE | 0 | Powerdown | R7 | |||
CLKout11_TYPE | 0 | Powerdown | R8 | |||
CLKout2_TYPE | 0 | Powerdown | R6 | 27:24 [4] | ||
CLKout6_TYPE(1) | 8 | LVCMOS (Norm/Norm) | R7 | |||
CLKout10_TYPE | 0 | Powerdown | R8 | |||
CLKout1_TYPE | 0 | Powerdown | R6 | 23:20 [4] | ||
CLKout5_TYPE | 0 | Powerdown | R7 | |||
CLKout9_TYPE | 0 | Powerdown | R8 | |||
CLKout0_TYPE | 0 | Powerdown | R6 | 19:16 [4] | ||
CLKout4_TYPE | 0 | Powerdown | R7 | |||
CLKout8_TYPE | 1 | LVDS | R8 | |||
Osc Buffer Control Mode | OSCout1_TYPE | 2 | 1600 mVpp LVPECL | Set LVPECL amplitude | R10 | 31:30 [2] |
OSCout0_TYPE | 1 | LVDS | OSCout0 default clock output | R10 | 27:24 [4] | |
EN_OSCout1 | 0 | Disabled | Disable OSCout1 output buffer | R10 | 23 | |
EN_OSCout0 | 1 | Enabled | Enable OSCout0 output buffer | R10 | 22 | |
OSCout1_MUX | 0 | Bypass Divider | Select OSCout divider for OSCout1 or bypass | R10 | 21 | |
OSCout0_MUX | 0 | Bypass Divider | Select OSCout divider for OSCout0 or bypass | R10 | 20 | |
OSCout_DIV | 0 | Divide-by-8 | OSCout divider value | R10 | 18:16 [3] | |
SYNC Control | NO_SYNC_CLKout10_11 | 0 | Will sync | Disable individual clock groups from becoming synchronized. | R11 | 25 |
NO_SYNC_CLKout8_9 | 1 | Will not sync | R11 | 24 | ||
NO_SYNC_CLKout6_7 | 1 | Will not sync | R11 | 23 | ||
NO_SYNC_CLKout4_5 | 0 | Will sync | R11 | 22 | ||
NO_SYNC_CLKout2_3 | 0 | Will sync | R11 | 21 | ||
NO_SYNC_CLKout0_1 | 0 | Will sync | R11 | 20 | ||
SYNC_POL_INV | 1 | Logic Low | Sets the polarity of the SYNC pin when input. (Use for software SYNC) | R11 | 16 | |
SYNC_TYPE | 1 | Input /w Pull-up | SYNC IO pin type | R11 | 13:12 [2] | |
Other Mode Control | EN_PLL_XTAL | 0 | Disabled | Enable Crystal oscillator for OSCin | R11 | 5 |
LD_MUX | 3 | Reserved | Ftest/LD pin selection when output | R12 | 31:27 [5] | |
LD_TYPE | 3 | Output (Push-Pull) | LD IO pin type | R12 | 26:24 [3] | |
SYNC_PLL_DLD | 0 | No effect | When set, force SYNC until PLL locks | R12 | 23 | |
READBACK_TYPE | 3 | Output (Push-Pull) | Readback Pin Type | R13 | 26:24 [3] | |
GPout | GPout0 | 2 | Weak pull-down | GPout0 output state | R13 | 18:16 [3] |
GPout1 | 2 | Weak pull-down | GPout1 output state | R14 | 28:26 [3] | |
PLL Control | PLL_C4_LF | 0 | 10 pF | PLL integrated capacitor C4 value | R24 | 31:28 [4] |
PLL_C3_LF | 0 | 10 pF | PLL integrated capacitor C3 value | R24 | 27:24 [4] | |
PLL_R4_LF | 0 | 200 Ω | PLL integrated resistor R4 value | R24 | 22:20 [3] | |
PLL_R3_LF | 0 | 200 Ω | PLL integrated resistor R3 value | R24 | 18:16 [3] | |
EN_PLL_REF_2X | 0 | Disabled, 1x | Doubles reference frequency of PLL. | R26 | 29 | |
PLL_CP_GAIN | 3 | 3.2 mA | PLL Charge Pump Gain | R26 | 27:26 [2] | |
PLL_DLD_CNT | 8192 | 8192 Counts | Number of PDF cycles which phase error must be within DLD window before LD state is asserted. | R26 | 19:6 [14] | |
PLL_R | 4 | Divide-by-4 | PLL R Divider (1 to 4095) | R28 | 31:20 [12] | |
OSCin_FREQ | 7 | 448 to 500 MHz | OSCin frequency range | R29 | 26:24 [3] | |
PLL_N_CAL | 48 | Divide-by-48 | Must be programmed to PLL_N value. | R29 | 22:5 [18] | |
PLL_P | 2 | Divide-by-2 | PLL N Divider Prescaler (2 to 8) | R30 | 26:24 [3] | |
PLL_N | 48 | Divide-by-48 | PLL N Divider (1 to 262143) | R30 | 22:5 [18] | |
uWire | uWire_LOCK | 0 | Writable | The values of registers R0 to R30 are lockable | R31 | 5 |