JAJSO87 may 2023 LMK04368-EP
PRODUCTION DATA
The following section details the fields of each register, the Power-On-Reset Defaults, and specific descriptions of each bit.
In some cases similar fields are located in multiple registers. In this case specific outputs may be designated as X or Y. In these cases, the X represents even numbers from 0 to 12 and the Y represents odd numbers from 1 to 13. In the case where X and Y are both used in a bit name, then Y = X + 1.
Address Range | Functionality | Description |
---|---|---|
0x00 to 0x00D | System Functions | Read only information such as product and vendor ID, etc |
0x100 to 0x137 | Device Clock and SYSREF clock Output Controls | For each of the seven clock output pairs, a group of registers control each individual output's behavior. CLKout0_1: 0x100 to 0x107 CLKout2_3: 0x108 to 0x10F CLKout4_5: 0x110 to 0x117 CLKout6_7: 0x118 to 0x11F CLKout8_9: 0x120 to 0x127 CLKout10_11: 0x128 to 0x12F CLKout12_13: 0x130 to 0x137 |
0x138 and 0x145 | SYSREF, SYNC, and Device Config | Settings for SYSREF and SYNC configurations such as SYSREF divide value, delay, pulse count, etc. Sets VCO and OSCout muxes output signal and OSCout's output format. Powerdown registers for device components (except CLKoutX_Y) |
0x146 to 0x149 | CLKin Control Control | Controls different behaviors for CLKinX such as selecting input clock source, enabling CLKinX, etc. |
0x14A | RESET_MUX, RESET_TYPE | Controls the RESET_MUX and RESET_TYPE |
0x14B to 0x152 | Holdover | Controls different behaviors when enabling holdover |
0x153 to 0x15F and 0x177 | PLL1 Configuration | Controls different behaviors for PLL1 such as setting and syncing the R and N dividers, calibrating PLL1, etc. |
0x160 to 0x173 | PLL2 Configuration | Controls different behaviors for PLL2 such as setting and syncing the R and N dividers, calibrating PLL2, etc. |
0x174 to 0x555 (except 0x177) | Misc Registers | Readback access for different registers and SPI Lock |