JAJSER5A February   2018  – April 2018 LMK05028

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      ブロック概略図
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
    2. 6.1 Device Start-Up Modes
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Diagrams
    7. 7.7 Typical Characteristics
  8. 8 Parameter Measurement Information
    1. 8.1 Output Clock Test Configurations
  9. 9 Detailed Description
    1. 9.1 Overview
      1. 9.1.1 ITU-T G.8262 (SyncE) Standards Compliance
    2. 9.2 Functional Block Diagrams
      1. 9.2.1 PLL Architecture Overview
      2. 9.2.2 3-Loop Mode
        1. 9.2.2.1 PLL Output Clock Phase Noise Analysis in 3-Loop Mode
      3. 9.2.3 2-Loop REF-DPLL Mode
      4. 9.2.4 2-Loop TCXO-DPLL Mode
      5. 9.2.5 PLL Configurations for Common Applications
    3. 9.3 Feature Description
      1. 9.3.1  Oscillator Input (XO_P/N)
      2. 9.3.2  TCXO/OCXO Input (TCXO_IN)
      3. 9.3.3  Reference Inputs (INx_P/N)
      4. 9.3.4  Clock Input Interfacing and Termination
      5. 9.3.5  Reference Input Mux Selection
        1. 9.3.5.1 Automatic Input Selection
        2. 9.3.5.2 Manual Input Selection
      6. 9.3.6  Hitless Switching
      7. 9.3.7  Gapped Clock Support on Reference Inputs
      8. 9.3.8  Input Clock and PLL Monitoring, Status, and Interrupts
        1. 9.3.8.1 XO Input Monitoring
        2. 9.3.8.2 TCXO Input Monitoring
        3. 9.3.8.3 Reference Input Monitoring
          1. 9.3.8.3.1 Reference Validation Timer
          2. 9.3.8.3.2 Amplitude Monitor
          3. 9.3.8.3.3 Missing Pulse Monitor (Late Detect)
          4. 9.3.8.3.4 Runt Pulse Monitor (Early Detect)
          5. 9.3.8.3.5 Frequency Monitoring
          6. 9.3.8.3.6 Phase Valid Monitor for 1-PPS Inputs
        4. 9.3.8.4 PLL Lock Detectors
        5. 9.3.8.5 Tuning Word History
        6. 9.3.8.6 Status Outputs
        7. 9.3.8.7 Interrupt
      9. 9.3.9  PLL Channels
        1. 9.3.9.1  PLL Frequency Relationships
        2. 9.3.9.2  Analog PLL (APLL)
        3. 9.3.9.3  APLL XO Doubler
        4. 9.3.9.4  APLL Phase Frequency Detector (PFD) and Charge Pump
        5. 9.3.9.5  APLL Loop Filter
        6. 9.3.9.6  APLL Voltage Controlled Oscillator (VCO)
          1. 9.3.9.6.1 VCO Calibration
        7. 9.3.9.7  APLL VCO Post-Dividers (P1, P2)
        8. 9.3.9.8  APLL Fractional N Divider (N) With SDM
        9. 9.3.9.9  REF-DPLL Reference Divider (R)
        10. 9.3.9.10 TCXO/OCXO Input Doubler and M Divider
        11. 9.3.9.11 TCXO Mux
        12. 9.3.9.12 REF-DPLL and TCXO-DPLL Time-to-Digital Converter (TDC)
        13. 9.3.9.13 REF-DPLL and TCXO-DPLL Loop Filter
        14. 9.3.9.14 REF-DPLL and TCXO-DPLL Feedback Dividers
      10. 9.3.10 Output Clock Distribution
      11. 9.3.11 Output Channel Muxes
        1. 9.3.11.1 TCXO/Ref Bypass Mux
      12. 9.3.12 Output Dividers
      13. 9.3.13 Clock Outputs (OUTx_P/N)
        1. 9.3.13.1 AC-Differential Output (AC-DIFF)
        2. 9.3.13.2 HCSL Output
        3. 9.3.13.3 LVCMOS Output (1.8 V, 2.5 V)
        4. 9.3.13.4 Output Auto-Mute During LOL or LOS
      14. 9.3.14 Glitchless Output Clock Start-Up
      15. 9.3.15 Clock Output Interfacing and Termination
      16. 9.3.16 Output Synchronization (SYNC)
      17. 9.3.17 Zero-Delay Mode (ZDM) Configuration
      18. 9.3.18 PLL Cascading With Internal VCO Loopback
    4. 9.4 Device Functional Modes
      1. 9.4.1 Device Start-Up Modes
        1. 9.4.1.1 EEPROM Mode
        2. 9.4.1.2 ROM Mode
      2. 9.4.2 PLL Operating Modes
        1. 9.4.2.1 Free-Run Mode
        2. 9.4.2.2 Lock Acquisition
        3. 9.4.2.3 Locked Mode
        4. 9.4.2.4 Holdover Mode
      3. 9.4.3 PLL Start-Up Sequence
      4. 9.4.4 Digitally-Controlled Oscillator (DCO) Mode
        1. 9.4.4.1 DCO Frequency Step Size
        2. 9.4.4.2 DCO Direct-Write Mode
      5. 9.4.5 Zero-Delay Mode (ZDM)
      6. 9.4.6 Cascaded PLL Operation
    5. 9.5 Programming
      1. 9.5.1 Interface and Control
      2. 9.5.2 I2C Serial Interface
        1. 9.5.2.1 I2C Block Register Transfers
      3. 9.5.3 SPI Serial Interface
        1. 9.5.3.1 SPI Block Register Transfer
      4. 9.5.4 Register Map Generation
      5. 9.5.5 General Register Programming Sequence
      6. 9.5.6 EEPROM Programming Flow
        1. 9.5.6.1 EEPROM Programming Using Register Commit (Method #1)
          1. 9.5.6.1.1 Write SRAM Using Register Commit
          2. 9.5.6.1.2 Program EEPROM
        2. 9.5.6.2 EEPROM Programming Using Direct SRAM Writes (Method #2)
          1. 9.5.6.2.1 Write SRAM Using Direct Writes
      7. 9.5.7 Read SRAM
      8. 9.5.8 Read EEPROM
      9. 9.5.9 EEPROM Start-Up Mode Default Configuration
    6. 9.6 Register Maps
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Device Start-Up Sequence
      2. 10.1.2 Power Down (PDN) Pin
      3. 10.1.3 Power Rail Sequencing, Power Supply Ramp Rate, and Mixing Supply Domains
        1. 10.1.3.1 Mixing Supplies
        2. 10.1.3.2 Power-On Reset (POR) Circuit
        3. 10.1.3.3 Powering Up From a Single-Supply Rail
        4. 10.1.3.4 Power Up From Split-Supply Rails
        5. 10.1.3.5 Non-Monotonic or Slow Power-Up Supply Ramp
      4. 10.1.4 Slow or Delayed XO Start-Up
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curves
    3. 10.3 Do's and Don'ts
  11. 11Power Supply Recommendations
    1. 11.1 Power Supply Bypassing
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
    3. 12.3 Thermal Reliability
  13. 13デバイスおよびドキュメントのサポート
    1. 13.1 デバイス・サポート
      1. 13.1.1 Clock Architect
      2. 13.1.2 TICS Pro
    2. 13.2 ドキュメントのサポート
      1. 13.2.1 関連資料
    3. 13.3 ドキュメントの更新通知を受け取る方法
    4. 13.4 コミュニティ・リソース
    5. 13.5 商標
    6. 13.6 静電気放電に関する注意事項
    7. 13.7 Glossary
  14. 14メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.5 Electrical Characteristics

Over Recommended Operating Conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Power Supply Characteristics
IDD_IN0, IDD_IN1, IDD_IN3 Core Supply Current
(VDD_INx)		 3.5 10 mA
IDD_IN2 Core Supply Current
(VDD_IN2)		 6 14 mA
IDD_XO Core Supply Current
(VDD_XO)		 25 33 mA
IDD_TCXO Core Supply Current
(VDD_TCXO)		 Configuration A(1) 1 4 mA
Configuration B(2) 6 9 mA
IDD_PLL1 Core Supply Current
(VDD_PLL1)		 Configuration A(1) 160 188 mA
Configuration B(2) 185 217 mA
IDD_PLL2 Core Supply Current
(VDD_PLL2)		 Configuration A(1) 138 160 mA
Configuration B(2) 160 187 mA
IDD_DIG Core Supply Current
(VDD_DIG)		 Configuration A(1) 34 59 mA
Configuration B(2) 42 70 mA
IDDO_x Output Supply Current(9)
(VDDO_x = 3.3 V ± 5%)		 AC-LVDS 22 28 mA
AC-CML 24 32 mA
AC-LVPECL 27 34 mA
HCSL 33 42 mA
IDDO_x Output Supply Current(10)
(VDDO_x = 3.3 V ± 5%)		 AC-LVDS (x2) 32 40 mA
AC-CML (x2) 37 45 mA
AC-LVPECL (x2) 41 51 mA
HCSL (x2) 55 67 mA
IDDPDN Total Supply Current
(all VDD and VDDO pins, 3.3 V)		 Device powered-down (PDN pin held low) 40 mA
Reference Input Characteristics (INx)
fIN Input frequency range(3)
Differential input(4) 5 750 MHz
LVCMOS input 1E-6 250
VIN-SE Single-ended input voltage swing LVCMOS input, DC-coupled to INx_P 1 V
VIDpp Differential input voltage swing,
peak-peak (|VP – VN|)(14) 		Differential input 0.4 2 V
dV/dt Input slew rate(3) 0.2 V/ns
IIN Input leakage 50-Ω and 100-Ω internal terminations disabled -350 350 µA
CIN Input capacitance Single-ended, each pin 2 pF
XO Input Characteristics (XO)
fCLK Input frequency range(3) 10 100 MHz
VIN-SE Single-ended input voltage swing LVCMOS input, DC-coupled to XO_P 1 2.6 V
VIDpp Differential input voltage swing,
peak-peak (|VP – VN|)(14) 		Differential input 0.4 2 V
dV/dt Input slew rate(3) 0.2 V/ns
IDC Input duty cycle 40 60 %
IIN Input leakage 50-Ω and 100-Ω internal terminations disabled -350 350 µA
CIN Input capacitance Single-ended, each pin 1 pF
TCXO/OCXO Input Characteristics (TCXO_IN)
fTCXO Input frequency(3) 10 54 MHz
VIN Input voltage swing AC-coupled 0.8 1.3 V
VBIAS Input bias voltage Weak internal bias 0.6 V
dV/dt Input slew rate(3) 0.2 V/ns
IDC Input duty cycle 40 60 %
CIN Input capacitance 10 pF
APLL/VCO Charateristics
fVCO1 VCO1 Frequency range 4.8 5.4 GHz
fVCO2 VCO2 Frequency range 5.5 6.2 GHz
1.8-V LVCMOS Output Characteristics (OUTx)
fOUT Output frequency(3) 1E-6 200 MHz
VOH Output high voltage IOH = 1 mA 1.2 V
VOL Output low voltage IOL = 1 mA 0.4 V
IOH Output high current -23 mA
IOL Output low current 24 mA
tR/tF Output rise/fall time(3) 20% to 80% 250 ps
tSK Output-to-output skew(3) Same post divider, output divide values, and output type 100 ps
Same post divider, output divide values, LVCMOS-to-DIFF 1.5 ns
PNFLOOR Output phase noise floor
(fOFFSET > 10 MHz)		 66.66 MHz -155 dBc/Hz
ODC Output duty cycle(3)(12) 45 55 %
ROUT Output impedance 50 Ω
2.5-V LVCMOS Output Characteristics (OUTx)
fOUT Output frequency(3) 1E-6 200 MHz
VOH Output high voltage IOH = 1 mA 1.9 V
VOL Output low voltage IOL = 1 mA 0.525 V
IOH Output high current -48 mA
IOL Output low current 55 mA
tR/tF Output rise/fall time(3) 20% to 80% 250 ps
tSK Output-to-output skew(3) Same post divider, output divide values, and output type 100 ps
Same post divider, output divide values, LVCMOS-to-DIFF 1.5 ns
PNFLOOR Output phase noise floor
(fOFFSET > 10 MHz)		 66.66 MHz -155 dBc/Hz
ODC Output duty cycle(3)(12) 45 55 %
ROUT Output impedance 50 Ω
AC-LVDS Output Characteristics (OUTx)
fOUT Output frequency(3)(5) 750 MHz
VOD Output voltage swing (VOH - VOL) fOUT > 25 MHz 250 400 450 mV
VODpp Differential output voltage swing,
peak-to-peak		 2×VOD V
VOS Output common mode 100 430 mV
tSK Output-to-output skew(3) Same post divider, output divide values, and output type 100 ps
tR/tF Output rise/fall time(3) 20% to 80%, < 300 MHz 225 350 ps
± 100 mV around center point, ≥ 300 MHz 75 150 ps
PNFLOOR Output phase noise floor
(fOFFSET > 10 MHz)		 156.25 MHz -160 dBc/Hz
ODC Output duty cycle(3)(12) 45 55 %
AC-CML Output Characteristics (OUTx)
fOUT Output frequency(3)(5) 750 MHz
VOD Output voltage swing (VOH - VOL) 400 600 800 mV
VODpp Differential output voltage swing,
peak-to-peak		 2×VOD V
VOS Output common mode 150 550 mV
tSK Output-to-output skew(3) Same post divider, output divide values, and output type 100 ps
tR/tF Output rise/fall time(3) 20% to 80%, < 300 MHz 150 300 ps
± 100 mV around center point, ≥ 300 MHz 50 125 ps
PNFLOOR Output duty cycle(3)(12) 156.25 MHz -160 dBc/Hz
ODC Output duty cycle(3) 45 55 %
AC-LVPECL Output Characteristics (OUTx)
fOUT Output frequency(3)(5) 750 MHz
VOD Output voltage swing (VOH - VOL) 500 850 1000 mV
VODpp Differential output voltage swing,
peak-to-peak		 2×VOD V
VOS Output common mode 0.3 0.7 V
tSK Output-to-output skew(3) Same post divider, output divide values, and output type 100 ps
tR/tF Output rise/fall time(3) 20% to 80%, < 300 MHz 150 300 ps
± 100 mV around center point, ≥ 300 MHz 25 100 ps
PNFLOOR Output phase noise floor
(fOFFSET > 10 MHz)		 156.25 MHz -162 dBc/Hz
ODC Output duty cycle(3)(12) 45 55 %
HCSL Output Characteristics (OUTx)
fOUT Output frequency(3)(5) 400 MHz
VOH Output high voltage 600 880 mV
VOL Output low voltage -150 150 mV
tSK Output-to-output skew(3) Same post divider, output divide values, and output type 100 ps
dV/dt Output slew rate(3) Measured from -150 mV to +150 mV on the differential waveform  2.5 6 V/ns
PNFLOOR Output phase noise floor (fOFFSET > 10 MHz) 100 MHz -158 dBc/Hz
ODC Output duty cycle(3)(12) 100 MHz 45 55 %
3-Level Logic Input Characteristics (HW_SW_CTRL, STATUS[1:0])
VIH Input high voltage 1.4 V
VIM Input mid voltage Input floating with internal bias and PDN pulled low 0.7 0.9 V
VIL Input low voltage 0.4 V
IIH Input high current VIH = VDD -40 40 µA
IIL Input low current VIL = GND -40 40 µA
CIN Input capacitance 2 pF
2-Level Logic Input Characteristics (PDN, GPIO[6:0], SDI, SCK, SCS, INSELx_[1:0])
VIH Input high voltage 1.2 V
VIL Input low voltage 0.6 V
IIH Input high current VIH = VDD -40 40 µA
IIL Input low current VIL = GND -40 40 µA
CIN Input capacitance 2 pF
Logic Output Characteristics (STATUS[1:0], GPIO[6:5], SDO)
VOH Output high voltage IOH = 1 mA 1.2 V
VOL Output low voltage IOL = 1 mA 0.6 V
tR/tF Output rise/fall time 20% to 80%, LVCMOS mode, 1 kΩ to GND 500 ps
SPI Timing Requirements (SDI, SCK, SCS, SDO)
fSCK SPI clock rate 20 MHz
t1 SCS to SCK setup time 10 ns
t2 SDI to SCK setup time 10 ns
t3 SDI to SCK hold time 10 ns
t4 SCK high time 25 ns
t5 SCK low time 25 ns
t6 SCK to SDO valid read-back data 10 ns
t7 SCS pulse width 20 ns
t8 SDI to SCK hold time 10 ns
I2C Interface Characteristics (SDA, SCL)
VIH Input high voltage 1.2 V
VIL Input low voltage 0.5 V
IIH Input leakage -15 15 µA
CIN Input capacitance 2 pF
VOL Output low voltage IOL = 3 mA 0.3 V
fSCL I2C clock rate Standard 100 kHz
Fast mode 400 kHz
tSU(START) START condition setup time SCL high before SDA low 0.6 µs
tH(START) START condition hold time SCL low after SDA low 0.6 µs
tW(SCLH) SCL pulse width high 0.6 µs
tW(SCLL) SCL pulse width low 1.3 µs
tSU(SDA) SDA setup time 100 ns
tH(SDA) SDA hold time SDA valid after SCL low 0 0.9 µs
tR(IN) SDA/SCL input rise time 300 ns
tF(IN) SDA/SCL input fall time 300 ns
tF(OUT) SDA output fall time CBUS ≤ 400 pF 300 ns
tSU(STOP) STOP condition setup time 0.6 µs
tBUS Bus free time between STOP and START 1.3 µs
Other Characteristics
tPHO Input-to-output phase offset Zero delay mode 2 ns
PSNR Spur induced by power supply noise (VN = 50 mVpp)(6)(7) VDDO_x = 2.5 V or 3.3 V, AC-DIFF or HCSL output -70 dBc
VDDO_x = 2.5 V, LVCMOS output -55
PSNR Spur induced by power supply noise (VN = 25 mVpp)(6)(7) VDDO_x = 1.8 V, AC-DIFF or HCSL output -70
VDDO_x = 1.8 V, LVCMOS output -45
SPUR Spur level due to output-to-output crosstalk (adjacent channels)(7) fOUTx = 156.25 MHz, fOUTy = 155.52 MHz, AC-DIFF or HCSL (same output type for both channels) -75 dBc
PLL Clock Output Performance Characteristics
RJ RMS phase jitter
(12 kHz to 20 MHz)
156.25 MHz AC-DIFF or HCSL output, fXO = 48.0048 MHz 150 250 fs RMS
PNTDC Output close-in phase noise
(fOFFSET = 100 Hz)		 122.88 MHz AC-DIFF or HCSL, 3-loop mode, fXO = 48.0048 MHz, fTCXO = 10 MHz, fTCXO-TDC = 20 MHz, BWREF = 5 Hz, BWTCXO = 400 Hz -112 dBc/Hz
BW DPLL bandwidth range(8) Programmed bandwidth setting 0.01 to 4000 Hz
JPK DPLL closed-loop jitter peaking(13) fIN = 25 MHz, fOUT = 10 MHz, DPLL BW = 0.1 Hz or 10 Hz 0.1 dB
JTOL Jitter tolerance Jitter modulation = 10 Hz,
25.78125 Gbps		 6455 UI p-p
tHITLESS Phase transient during hitless switch Valid for a single switchover event between two clock inputs at the same frequency ± 50 ps
fHITLESS Frequency transient during hitless switch Valid for a single switchover event between two clock inputs at the same frequency ± 10 ppb
tSTARTUP Initial PLL clock start-up time(11) From rising edge of PDN to free-running output clocks 20 ms
(1) Configuration A (All blocks on except TCXO_IN and both TCXO-DPLLs): fIN[0:3] = 25 MHz, fXO = 48.0048 MHz, TCXO_IN disabled. Both DPLL[1:2] in 2-loop mode, fVCO1 = 5 GHz, fVCO2 = 5.5296 GHz, PLL1_P1 = 8, PLL2_P1 = 9.
(2) Configuration B (All blocks on): fIN[0:3] = 25 MHz, fXO = 48.0048 MHz, fTCXO = 10 MHz. Both DPLL[1:2] in 3-loop mode, fVCO1 = 5 GHz, fVCO2 = 5.5296 GHz, PLL1_P1 = 8, PLL2_P1 = 9.
(3) Parameter is specified by characterization and is not tested in production. 
(4) For a differential input clock below 5 MHz, TI recommends to disable the differential input amplitude monitor and enable at least one other monitor (frequency, window detectors) to validate the input clock.  Otherwise, consider using an LVCMOS clock for an input below 5 MHz.
(5) An output frequency over the fOUT max spec is possible, but the output swing may be less than the VOD min spec.
(6) PSNR is the single-sideband spur level (in dBc) measured when sinusoidal noise with ampitude VN and frequency between 100 kHz and 1 MHz is injected onto VDD and VDDO_x pins.
(7) DJSPUR (ps pk-pk) = [2 × 10(dBc/20) / (π × fOUT) × 1E6], where dBc is the PSNR or SPUR level (in dBc) and fOUT is the output frequency (in MHz).
(8) Actual loop bandwidth may be lower. Applies to REF-DPLL and TCXO-DPLL. The valid loop bandwidth range may be constrained by the DPLL loop mode and REF-TDC and/or TCXO-TDC frequencies used in a given configuration. 
(9) IDDO_x includes supply current for output divider and one output driver with fOUT = 156.25 MHz or 122.88 MHz.
(10) IDDO_x includes supply current for output divider and two output drivers with fOUT = 156.25 MHz or 122.88 MHz.
(11) Assumes XO input clock is stable in frequency and amplitude before rising edge of PDN, PLLs start-up using parallel calibration mode, VCO wait timers set to 0.4 ms, PLL wait timers set to 3 ms, and outputs auto-mute during APLL lock only (DPLL auto-mute options disabled).
(12) Parameter is specified for PLL outputs divided from either VCO domain.
(13) The TICS Pro software configures the closed-loop jitter peaking for 0.1 dB or less based on the programmed DPLL bandwidth setting.
(14) Minimum limit applies for the minimum setting of the differential input amplitude monitor.