JAJSS37L November   2001  – February 2025 LP2992

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Output Enable
      2. 6.3.2 Dropout Voltage
      3. 6.3.3 Current Limit
        1. 6.3.3.1 Current Limit (Legacy Chip)
        2. 6.3.3.2 Current Limit (New Chip)
      4. 6.3.4 Undervoltage Lockout (UVLO)
      5. 6.3.5 Output Pulldown
      6. 6.3.6 Thermal Shutdown
    4. 6.4 Device Functional Modes
      1. 6.4.1 Normal Operation
      2. 6.4.2 Dropout Operation
      3. 6.4.3 Disabled
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Estimating Junction Temperature
      2. 7.1.2 Input and Output Capacitor Requirements
      3. 7.1.3 Noise Bypass Capacitor (CBYPASS)
      4. 7.1.4 Power Dissipation (PD)
      5. 7.1.5 Recommended Capacitor Types
        1. 7.1.5.1 Recommended Capacitors (Legacy Chip)
          1. 7.1.5.1.1 Tantalum Capacitors (Legacy Chip)
        2. 7.1.5.2 Recommended Capacitors (New Chip)
      6. 7.1.6 Reverse Current
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 ON/OFF Operation
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Examples
  9. 8 Device and Documentation Support
    1. 8.1 Device Nomenclature
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 サポート・リソース
    5. 8.5 Trademarks
    6. 8.6 静電気放電に関する注意事項
    7. 8.7 用語集
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5.4 Thermal Information

THERMAL METRIC (2) (1) Legacy Chip Only Legacy Chip New Chip UNIT
NGD (WSON) (3) DBV (SOT23-5) DBV (SOT23-5)
6 PINS 5 PINS 5 PINS
RθJA Junction-to-ambient thermal resistance 72.3 169.7 178.6 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 81.6 122.6 77.9 °C/W
RθJB Junction-to-board thermal resistance 39.5 29.9 47.2 °C/W
ψJT Junction-to-top characterization parameter 2 16.7 15.9 °C/W
ψJB Junction-to-board characterization parameter 39.2 29.4 46.9 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 11.6 − − °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application note.
(2) Thermal performance results are based on the JEDEC standard of 2s2p PCB configuration. These thermal metric parameters can be further improved by 35-55% based on thermally optimized PCB layout designs. See the analysis of the Impact of board layout on LDO thermal performance application report.
(3) The PCB for the NGD (WSON) package RθJA includes two (2) thermal vias under the exposed thermal pad per EIA/JEDEC JESD51-5.