JAJSMR5 January   2022 LP5861

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Device Comparison
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Analog Dimming (Current Gain Control)
      2. 8.3.2 PWM Dimming
      3. 8.3.3 ON and OFF Control
      4. 8.3.4 Data Refresh Mode
      5. 8.3.5 Full Addressable SRAM
      6. 8.3.6 Protections and Diagnostics
    4. 8.4 Device Functional Modes
    5. 8.5 Programming
    6. 8.6 Register Maps
      1. 8.6.1 CONFIG Registers
      2. 8.6.2 GROUP Registers
      3. 8.6.3 DOTGROUP Registers
      4. 8.6.4 DOTONOFF Registers
      5. 8.6.5 FAULT Registers
      6. 8.6.6 RESET Registers
      7. 8.6.7 DC Registers
      8. 8.6.8 PWM Registers
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Application
      2. 9.2.2 Design Requirements
      3. 9.2.3 Detailed Design Procedure
      4. 9.2.4 Program Procedure
      5. 9.2.5 Application Performance Plots
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 サポート・リソース
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.6.6 RESET Registers

Table 8-41 lists the RESET registers, including LOD_CLR registers, LSD_CLR registers and Reset registers. All register offset addresses not listed in Table 8-41 must be considered as reserved locations and the register contents must not be modified.

Table 8-41 RESET Registers
Address Acronym Register Name Section
A7h LOD_clear LOD flag clear register Go
A8h LSD_clear LSD flag clear register Go
A9h Reset Software reset register Go

8.6.6.1 LOD_clear Register (Address = A7h) [Default = 0h]

LOD_clear is shown in Figure 8-44 and described in Table 8-42.

Return to the Summary Table.

Figure 8-44 LOD_clear Register
7 6 5 4 3 2 1 0
RESERVED LOD_Clear
R-0h W-0h
Table 8-42 LOD_clear Register Field Descriptions
Bit Field Type Default Description
7-4 RESERVED R 0h Reserved
3-0 LOD_Clear W 0h Write Fh to clear all LOD indication bits

8.6.6.2 LSD_clear Register (Address = A8h) [Default = 0h]

LSD_clear is shown in Figure 8-45 and described in Table 8-43.

Return to the Summary Table.

Figure 8-45 LSD_clear Register
7 6 5 4 3 2 1 0
RESERVED LSD_Clear
R-0h W-0h
Table 8-43 LSD_clear Register Field Descriptions
Bit Field Type Default Description
7-4 RESERVED R 0h Reserved
3-0 LSD_Clear W 0h Write Fh to clear all LSD indication bits

8.6.6.3 Reset Register (Address = A9h) [Default = 0h]

Reset is shown in Figure 8-46 and described in Table 8-44.

Return to the Summary Table.

Figure 8-46 Reset Register
7 6 5 4 3 2 1 0
Reset
W-0h
Table 8-44 Reset Register Field Descriptions
Bit Field Type Default Description
7-0 Reset W 0h Write FFh to reset the device