JAJSG84B January   2016  – June 2018 LP8758-E0

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      概略回路図
      2.      効率と出力電流との関係
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 I2C Serial Bus Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
      1. 7.1.1 Buck Information
        1. 7.1.1.1 Operating Modes
        2. 7.1.1.2 Programmability
        3. 7.1.1.3 Features
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Overview
        1. 7.3.1.1 Transition between PWM and PFM Modes
        2. 7.3.1.2 Buck Converter Load Current Measurement
        3. 7.3.1.3 Spread-Spectrum Mode
      2. 7.3.2 Power-Up
      3. 7.3.3 Regulator Control
        1. 7.3.3.1 Enabling and Disabling
        2. 7.3.3.2 Changing Output Voltage
      4. 7.3.4 Device Reset Scenarios
      5. 7.3.5 Diagnosis and Protection Features
        1. 7.3.5.1 Warnings for Diagnosis (Interrupt)
          1. 7.3.5.1.1 Output Current Limit
          2. 7.3.5.1.2 Thermal Warning
        2. 7.3.5.2 Protection (Regulator Disable)
          1. 7.3.5.2.1 Short-Circuit and Overload Protection
          2. 7.3.5.2.2 Thermal Shutdown
        3. 7.3.5.3 Fault (Power Down)
          1. 7.3.5.3.1 Undervoltage Lockout
      6. 7.3.6 Digital Signal Filtering
    4. 7.4 Device Functional Modes
      1. 7.4.1 Modes of Operation
    5. 7.5 Programming
      1. 7.5.1 I2C-Compatible Interface
        1. 7.5.1.1 Data Validity
        2. 7.5.1.2 Start and Stop Conditions
        3. 7.5.1.3 Transferring Data
        4. 7.5.1.4 I2C-Compatible Chip Address
        5. 7.5.1.5 Auto Increment Feature
    6. 7.6 Register Maps
      1. 7.6.1 Register Descriptions
        1. 7.6.1.1  OTP_REV
        2. 7.6.1.2  BUCK0_CTRL1
        3. 7.6.1.3  BUCK0_CTRL2
        4. 7.6.1.4  BUCK1_CTRL1
        5. 7.6.1.5  BUCK1_CTRL2
        6. 7.6.1.6  BUCK2_CTRL1
        7. 7.6.1.7  BUCK2_CTRL2
        8. 7.6.1.8  BUCK3_CTRL1
        9. 7.6.1.9  BUCK3_CTRL2
        10. 7.6.1.10 BUCK0_VOUT
        11. 7.6.1.11 BUCK0_FLOOR_VOUT
        12. 7.6.1.12 BUCK1_VOUT
        13. 7.6.1.13 BUCK1_FLOOR_VOUT
        14. 7.6.1.14 BUCK2_VOUT
        15. 7.6.1.15 BUCK2_FLOOR_VOUT
        16. 7.6.1.16 BUCK3_VOUT
        17. 7.6.1.17 BUCK3_FLOOR_VOUT
        18. 7.6.1.18 BUCK0_DELAY
        19. 7.6.1.19 BUCK1_DELAY
        20. 7.6.1.20 BUCK2_DELAY
        21. 7.6.1.21 BUCK3_DELAY
        22. 7.6.1.22 RESET
        23. 7.6.1.23 CONFIG
        24. 7.6.1.24 INT_TOP
        25. 7.6.1.25 INT_BUCK_0_1
        26. 7.6.1.26 INT_BUCK_2_3
        27. 7.6.1.27 TOP_STAT
        28. 7.6.1.28 BUCK_0_1_STAT
        29. 7.6.1.29 BUCK_2_3_STAT
        30. 7.6.1.30 TOP_MASK
        31. 7.6.1.31 BUCK_0_1_MASK
        32. 7.6.1.32 BUCK_2_3_MASK
        33. 7.6.1.33 SEL_I_LOAD
        34. 7.6.1.34 I_LOAD_2
        35. 7.6.1.35 I_LOAD_1
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Application Components
          1. 8.2.2.1.1 Inductor Selection
          2. 8.2.2.1.2 Input Capacitor Selection
          3. 8.2.2.1.3 Output Capacitor Selection
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 デバイス・サポート
      1. 11.1.1 デベロッパー・ネットワークの製品に関する免責事項
    2. 11.2 ドキュメントのサポート
      1. 11.2.1 関連資料
    3. 11.3 ドキュメントの更新通知を受け取る方法
    4. 11.4 コミュニティ・リソース
    5. 11.5 商標
    6. 11.6 静電気放電に関する注意事項
    7. 11.7 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.3.3.1 Enabling and Disabling

The buck converter cores can be enabled when the device is in STANDBY or ACTIVE state. There are two ways for enable and disable the buck converter core cores:

  • Using BUCKx_CTRL1.EN_BUCKx register bit (when BUCKx_CTRL1.EN_PIN_CTRLx register bit is 0).
  • Using EN1/2 control pins (BUCKx_CTRL1.EN_BUCKx register bit is 1 and BUCKx_CTRL1.EN_PIN_CTRLx register bit is 1).

If the EN1/2 control pins are used for enable and disable, the delay from the control signal rising edge to start-up is set by BUCKx_DELAY.BUCKx_STARTUP_DELAY[3:0] bits and the delay from control signal falling edge to shutdown is set by BUCKx_DELAY.BUCKx_SHUTDOWN_DELAY[3:0] bits. The delays are valid only for EN1/2 signal and not for control with BUCKx_CTRL1.EN_BUCKx bit. The delay time implemented by EN1/2 has overall +/-10% timing accuracy.

The control of the converter cores (with 0 ms delays) is shown in Table 2.

Table 2. Regulator Control

CONTROL METHOD ROW EN_BUCKx BUCKx_CTRL1
EN_PIN_CTRLx		 BUCKx_CTRL1
EN_PIN_SELECTx		 BUCKx_CTRL1
EN_ROOF_FLOORx		 EN1 PIN EN2 PIN BUCKx
OUTPUT VOLTAGE
Enable/disable control with EN_BUCKx bit 1 0 Don't Care Don't Care Don't Care Don't Care Don't Care Disabled
2 1 0 Don't Care Don't Care Don't Care Don't Care BUCKx_VOUT.BUCKx_VSET[7:0]
Enable/disable control with EN1 pin 3 1 1 0 0 Low Don't Care Disabled
4 1 1 0 0 High Don't Care BUCKx_VOUT.BUCKx_VSET[7:0]
Enable/disable control with EN2 pin 5 1 1 1 0 Don't Care Low Disabled
6 1 1 1 0 Don't Care High BUCKx_VOUT.BUCKx_VSET[7:0]
Roof/floor control with EN1 pin 7 1 1 0 1 Low Don't Care BUCKx_FLOOR_VOUT.BUCKx_FLOOR_VSET[7:0]
8 1 1 0 1 High Don't Care BUCKx_VOUT.BUCKx_VSET[7:0]
Roof/floor control with EN2 pin 9 1 1 1 1 Don't Care Low BUCKx_FLOOR_VOUT.BUCKx_FLOOR_VSET[7:0]
10 1 1 1 1 Don't Care High BUCKx_VOUT.BUCKx_VSET[7:0]

The following configuration allows the enable/disable control using ENx pin:

  • BUCKx_CTRL1.EN_BUCKx = 1
  • BUCKx_CTRL1.EN_PIN_CTRLx = 1
  • BUCKx_CTRL1.EN_ROOF_FLOORx = 0
  • BUCKx_VOUT.BUCKx_VSET[7:0] = Required voltage when ENx is high
  • The enable pin for control is selected with BUCKx_CTRL1.EN_PIN_SELECTx

When the ENx pin is low, Table 2 row 3 (or 5) is valid, and the converter core is disabled. By setting ENx pin high, Table 2 row 4 (or 6) is valid, and the converter core is enabled with required voltage.

If a converter core is enabled all the time, and the ENx pin controls selection between two voltage level, the following configuration is used:

  • BUCKx_CTRL1.EN_BUCKx = 1
  • BUCKx_CTRL1.EN_PIN_CTRLx = 1
  • BUCKx_CTRL1.EN_ROOF_FLOORx = 1
  • BUCKx_VOUT.BUCKx_VSET[7:0] = Required voltage when ENx is high
  • The enable pin for control is selected with BUCKx_CTRL1.EN_PIN_SELECTx

When the ENx pin is low, Table 2 row 7 (or 9) is valid, and the core is enabled with a voltage defined by BUCKx_FLOOR_VOUT.BUCKx_FLOOR_VSET[7:0] bits. Setting the ENx pin high, Table 2 row 8 (or 10) is valid, and the core is enabled with a voltage defined by BUCKx_VOUT.BUCKx_VSET[7:0] bits.

If the core is controlled by I2C writings, the BUCKx_CTRL1.EN_PIN_CTRLx bit is set to 0. The enable/disable is controlled by the BUCKx_CTRL1.EN_BUCKx bit, and when the regulator is enabled, the output voltage is defined by the BUCKx_VOUT.BUCKx_VSET[7:0] bits. The Table 2 rows 1 and 2 are valid for I2C controlled operation (ENx pins are ignored).

The buck converter core is enabled by the ENx pin or by I2C writing as shown in Figure 9. The soft-start circuit limits the in-rush current during start-up. Output voltage increase rate is around 5 mV/μsec during soft-start. When the output voltage rises to approximately 0.3 V, the output voltage becomes slew-rate controlled. If there is a short circuit at the output, and the output voltage does not increase above a 0.35-V level in 1 ms, the converter core is disabled, and interrupt is set. When the output voltage reaches the powergood threshold level the INT_BUCK_x.BUCKx_PG_INT interrupt flag is set. The powergood interrupt flag can be masked using BUCK_x_MASK.BUCKx_PG_MASK bit.

The ENx input pins have integrated pull-down resistors. The pull-down resistors are enabled by default and host can disable those with CONFIG.ENx_PD bits.

LP8758-E0 Enable_Disable.gifFigure 9. Converter Core Enable and Disable