JAJSNS6A december   2022  – april 2023 MCF8315A

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Characteristics of the SDA and SCL bus for Standard and Fast mode
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Output Stage
      2. 7.3.2  Device Interface
        1. 7.3.2.1 Interface - Control and Monitoring
        2. 7.3.2.2 I2C Interface
      3. 7.3.3  Step-Down Mixed-Mode Buck Regulator
        1. 7.3.3.1 Buck in Inductor Mode
        2. 7.3.3.2 Buck in Resistor mode
        3. 7.3.3.3 Buck Regulator with External LDO
        4. 7.3.3.4 AVDD Power Sequencing from Buck Regulator
        5. 7.3.3.5 Mixed Mode Buck Operation and Control
        6. 7.3.3.6 Buck Under Voltage Protection
        7. 7.3.3.7 Buck Over Current Protection
      4. 7.3.4  AVDD Linear Voltage Regulator
      5. 7.3.5  Charge Pump
      6. 7.3.6  Slew Rate Control
      7. 7.3.7  Cross Conduction (Dead Time)
      8. 7.3.8  Speed Control
        1. 7.3.8.1 Analog Mode Speed Control
        2. 7.3.8.2 PWM Mode Speed Control
        3. 7.3.8.3 I2C based Speed Control
        4. 7.3.8.4 Frequency Mode Speed Control
        5. 7.3.8.5 Speed Profiles
          1. 7.3.8.5.1 Linear Speed Profiles
          2. 7.3.8.5.2 Staircase Speed Profile
          3. 7.3.8.5.3 Forward-Reverse Speed Profile
      9. 7.3.9  Starting the Motor Under Different Initial Conditions
        1. 7.3.9.1 Case 1 – Motor is Stationary
        2. 7.3.9.2 Case 2 – Motor is Spinning in the Forward Direction
        3. 7.3.9.3 Case 3 – Motor is Spinning in the Reverse Direction
      10. 7.3.10 Motor Start Sequence (MSS)
        1. 7.3.10.1 Initial Speed Detect (ISD)
        2. 7.3.10.2 Motor Resynchronization
        3. 7.3.10.3 Reverse Drive
          1. 7.3.10.3.1 Reverse Drive Tuning
        4. 7.3.10.4 Motor Start-up
          1. 7.3.10.4.1 Align
          2. 7.3.10.4.2 Double Align
          3. 7.3.10.4.3 Initial Position Detection (IPD)
            1. 7.3.10.4.3.1 IPD Operation
            2. 7.3.10.4.3.2 IPD Release Mode
            3. 7.3.10.4.3.3 IPD Advance Angle
          4. 7.3.10.4.4 Slow First Cycle Startup
          5. 7.3.10.4.5 Open loop
          6. 7.3.10.4.6 Transition from Open to Closed Loop
      11. 7.3.11 Closed Loop Operation
        1. 7.3.11.1 Closed loop accelerate
        2. 7.3.11.2 Speed PI Control
        3. 7.3.11.3 Current PI Control
        4. 7.3.11.4 Overmodulation
      12. 7.3.12 Motor Parameters
        1. 7.3.12.1 Motor Resistance
        2. 7.3.12.2 Motor Inductance
        3. 7.3.12.3 Motor Back-EMF constant
      13. 7.3.13 Motor Parameter Extraction Tool (MPET)
      14. 7.3.14 Anti-Voltage Surge (AVS)
      15. 7.3.15 Output PWM Switching Frequency
      16. 7.3.16 Active Braking
      17. 7.3.17 PWM Modulation Schemes
      18. 7.3.18 Dead Time Compensation
      19. 7.3.19 Motor Stop Options
        1. 7.3.19.1 Coast (Hi-Z) Mode
        2. 7.3.19.2 Recirculation Mode
        3. 7.3.19.3 Low-Side Braking
        4. 7.3.19.4 High-Side Braking
        5. 7.3.19.5 Active Spin-Down
        6. 7.3.19.6 Align Braking
      20. 7.3.20 FG Configuration
        1. 7.3.20.1 FG Output Frequency
        2. 7.3.20.2 FG Open-Loop and Lock Behavior
      21. 7.3.21 DC Bus Current Limit
      22. 7.3.22 Protections
        1. 7.3.22.1  VM Supply Undervoltage Lockout
        2. 7.3.22.2  AVDD Undervoltage Lockout (AVDD_UV)
        3. 7.3.22.3  BUCK Undervoltage Lockout (BUCK_UV)
        4. 7.3.22.4  VCP Charge Pump Undervoltage Lockout (CPUV)
        5. 7.3.22.5  Overvoltage Protection (OVP)
        6. 7.3.22.6  Overcurrent Protection (OCP)
          1. 7.3.22.6.1 OCP Latched Shutdown (OCP_MODE = 00b)
          2. 7.3.22.6.2 OCP Automatic Retry (OCP_MODE = 01b)
          3. 7.3.22.6.3 OCP Report Only (OCP_MODE = 10b)
          4. 7.3.22.6.4 OCP Disabled (OCP_MODE = 11b)
        7. 7.3.22.7  Buck Overcurrent Protection
        8. 7.3.22.8  Hardware Lock Detection Current Limit (HW_LOCK_ILIMIT)
          1. 7.3.22.8.1 HW_LOCK_ILIMIT Latched Shutdown (HW_LOCK_ILIMIT_MODE = 00xxb)
          2. 7.3.22.8.2 HW_LOCK_ILIMIT Automatic recovery (HW_LOCK_ILIMIT_MODE = 01xxb)
          3. 7.3.22.8.3 HW_LOCK_ILIMIT Report Only (HW_LOCK_ILIMIT_MODE = 1000b)
          4. 7.3.22.8.4 HW_LOCK_ILIMIT Disabled (HW_LOCK_ILIMIT_MODE= 1xx1b)
        9. 7.3.22.9  Thermal Warning (OTW)
        10. 7.3.22.10 Thermal Shutdown (TSD)
        11. 7.3.22.11 Motor Lock (MTR_LCK)
          1. 7.3.22.11.1 MTR_LCK Latched Shutdown (MTR_LCK_MODE = 00xxb)
          2. 7.3.22.11.2 MTR_LCK Automatic Recovery (MTR_LCK_MODE= 01xxb)
          3. 7.3.22.11.3 MTR_LCK Report Only (MTR_LCK_MODE = 1000b)
          4. 7.3.22.11.4 MTR_LCK Disabled (MTR_LCK_MODE = 1xx1b)
        12. 7.3.22.12 Motor Lock Detection
          1. 7.3.22.12.1 Lock 1: Abnormal Speed (ABN_SPEED)
          2. 7.3.22.12.2 Lock 2: Abnormal BEMF (ABN_BEMF)
          3. 7.3.22.12.3 Lock3: No-Motor Fault (NO_MTR)
        13. 7.3.22.13 MPET Faults
        14. 7.3.22.14 IPD Faults
    4. 7.4 Device Functional Modes
      1. 7.4.1 Functional Modes
        1. 7.4.1.1 Sleep Mode
        2. 7.4.1.2 Standby Mode
        3. 7.4.1.3 Fault Reset (CLR_FLT)
    5. 7.5 External Interface
      1. 7.5.1 DRVOFF Functionality
      2. 7.5.2 DAC outputs
      3. 7.5.3 Current Sense Output
      4. 7.5.4 Oscillator Source
        1. 7.5.4.1 External Clock Source
      5. 7.5.5 External Watchdog
    6. 7.6 EEPROM access and I2C interface
      1. 7.6.1 EEPROM Access
        1. 7.6.1.1 EEPROM Write
        2. 7.6.1.2 EEPROM Read
      2. 7.6.2 I2C Serial Interface
        1. 7.6.2.1 I2C Data Word
        2. 7.6.2.2 I2C Write Transaction
        3. 7.6.2.3 I2C Read Transaction
        4. 7.6.2.4 I2C Communication Protocol Packet Examples
        5. 7.6.2.5 I2C Clock Stretching
        6. 7.6.2.6 CRC Byte Calculation
    7. 7.7 EEPROM (Non-Volatile) Register Map
      1. 7.7.1 Algorithm_Configuration Registers
      2. 7.7.2 Fault_Configuration Registers
      3. 7.7.3 Hardware_Configuration Registers
      4. 7.7.4 Internal_Algorithm_Configuration Registers
    8. 7.8 RAM (Volatile) Register Map
      1. 7.8.1 Fault_Status Registers
      2. 7.8.2 System_Status Registers
      3. 7.8.3 Device_Control Registers
      4. 7.8.4 Algorithm_Control Registers
      5. 7.8.5 Algorithm_Variables Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Speed Input before VM Power-up
      2. 8.2.2 Application Curves
        1. 8.2.2.1 Motor startup
        2. 8.2.2.2 MPET
        3. 8.2.2.3 Dead time compensation
        4. 8.2.2.4 Auto handoff
        5. 8.2.2.5 Motor stop – recirculation mode
        6. 8.2.2.6 Anti voltage surge (AVS)
        7. 8.2.2.7 Real time variable tracking using DACOUT
  10. 9 Power Supply Recommendations
    1. 9.1 Bulk Capacitance
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Thermal Considerations
      1. 10.3.1 Power Dissipation
  12. 11Device and Documentation Support
    1. 11.1 サポート・リソース
    2. 11.2 Trademarks
    3. 11.3 静電気放電に関する注意事項
    4. 11.4 用語集
  13. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.7.4 Internal_Algorithm_Configuration Registers

Table 7-41 lists the memory-mapped registers for the Internal_Algorithm_Configuration registers. All register offset addresses not listed in Table 7-41 should be considered as reserved locations and the register contents should not be modified.

Table 7-41 INTERNAL_ALGORITHM_CONFIGURATION Registers
OffsetAcronymRegister NameSection
A0hINT_ALGO_1Internal Algorithm Configuration1INT_ALGO_1 Register (Offset = A0h) [Reset = 00000000h]
A2hINT_ALGO_2Internal Algorithm Configuration2INT_ALGO_2 Register (Offset = A2h) [Reset = 00000000h]

Complex bit access types are encoded to fit into small table cells. Table 7-42 shows the codes that are used for access types in this section.

Table 7-42 Internal_Algorithm_Configuration Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Write Type
WWWrite
Reset or Default Value
-nValue after reset or the default value

7.7.4.1 INT_ALGO_1 Register (Offset = A0h) [Reset = 00000000h]

INT_ALGO_1 is shown in Figure 7-81 and described in Table 7-43.

Return to the Summary Table.

Register to configure internal algorithm parameters1

Figure 7-81 INT_ALGO_1 Register
3130292827262524
RESERVEDACTIVE_BRAKE_SPEED__DELTA_LIMIT_EXITSPEED_PIN_GLITCH_FILTERFAST_ISD_ENISD_STOP_TIME
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
ISD_RUN_TIMEISD_TIMEOUTAUTO_HANDOFF_MIN_BEMFBRAKE_CURRENT_PERSIST
R/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
BRAKE_CURRENT_PERSISTMPET_IPD_CURRENT_LIMITMPET_IPD_FREQMPET_OPEN_LOOP_CURRENT_REF
R/W-0hR/W-0hR/W-0hR/W-0h
76543210
MPET_OPEN_LOOP_SPEED_REFMPET_OPEN_LOOP_SLEW_RATEREV_DRV_OPEN_LOOP_DEC
R/W-0hR/W-0hR/W-0h
Table 7-43 INT_ALGO_1 Register Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR/W0h Reserved
30-29ACTIVE_BRAKE_SPEED__DELTA_LIMIT_EXITR/W0h Difference between final speed and present speed below which active braking will be stopped
0h = 2.5%
1h = 5%
2h = 7.5%
3h = 10%
28-27SPEED_PIN_GLITCH_FILTERR/W0h Glitch filter applied on speed pin input
0h = No Glitch Filter
1h = 0.2 µs
2h = 0.5 µs
3h = 1.0 µs
26FAST_ISD_ENR/W0h Enable fast speed detection
0h = Disable Fast ISD
1h = Enable Fast ISD
25-24ISD_STOP_TIMER/W0h Persistence time for declaring motor has stopped
0h = 1 ms
1h = 5 ms
2h = 50 ms
3h = 100 ms
23-22ISD_RUN_TIMER/W0h Persistence time for declaring motor is running
0h = 1 ms
1h = 5 ms
2h = 50 ms
3h = 100 ms
21-20ISD_TIMEOUTR/W0h Timeout in case ISD is unable to reliably detect speed or direction
0h = 500ms
1h = 750 ms
2h = 1000 ms
3h = 2000 ms
19-17AUTO_HANDOFF_MIN_BEMFR/W0h Minimum BEMF for handoff (V)
0h = 0 mV
1h = 50 mV
2h = 100 mV
3h = 250 mV
4h = 500 mV
5h = 1000 mV
6h = 1250 mV
7h = 1500 mV
16-15BRAKE_CURRENT_PERSISTR/W0h Persistence time for current below threshold during low side brake
0h = 50 ms
1h = 100 ms
2h = 250 ms
3h = 500 ms
14-13MPET_IPD_CURRENT_LIMITR/W0h IPD current limit for MPET (A)
0h = 0.0625 A
1h = 0.3125 A
2h = 0.625 A
3h = 1.25 A
12-11MPET_IPD_FREQR/W0h Number of times IPD is executed for MPET
0h = 1
1h = 2
2h = 4
3h = 8
10-8MPET_OPEN_LOOP_CURRENT_REFR/W0h Open Loop Current Reference (A)
0h = 0.625 A
1h = 1.25 A
2h = 1.875 A
3h = 2.5 A
4h = 3.125 A
5h = 3.75 A
6h = Reserved
7h = Reserved
7-6MPET_OPEN_LOOP_SPEED_REFR/W0h Open Loop Speed Reference for MPET (% of MAXIMUM_SPEED)
0h = 15%
1h = 25%
2h = 35%
3h = 50%
5-3MPET_OPEN_LOOP_SLEW_RATER/W0h Open Loop Slew Rate for MPET (Hz/s)
0h = 0.1 Hz/s
1h = 0.5 Hz/s
2h = 1 Hz/s
3h = 2 Hz/s
4h = 3 Hz/s
5h = 5 Hz/s
6h = 10 Hz/s
7h = 20 Hz/s
2-0REV_DRV_OPEN_LOOP_DECR/W0h % of open loop acceleration to be applied during open loop deceleration in reverse drive
0h = 50%
1h = 60%
2h = 70%
3h = 80%
4h = 90%
5h = 100%
6h = 125%
7h = 150%

7.7.4.2 INT_ALGO_2 Register (Offset = A2h) [Reset = 00000000h]

INT_ALGO_2 is shown in Figure 7-82 and described in Table 7-44.

Return to the Summary Table.

Register to configure internal algorithm parameters2

Figure 7-82 INT_ALGO_2 Register
3130292827262524
RESERVEDRESERVED
R/W-0hR/W-0h
2322212019181716
RESERVED
R/W-0h
15141312111098
RESERVEDCL_SLOW_ACC
R/W-0hR/W-0h
76543210
CL_SLOW_ACCACTIVE_BRAKE_BUS_CURRENT_SLEW_RATEMPET_IPD_SELECTMPET_KE_MEAS_PARAMETER_SELECTIPD_HIGH_RESOLUTION_EN
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 7-44 INT_ALGO_2 Register Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR/W0h Reserved
30-10RESERVEDR/W0h Reserved
9-6CL_SLOW_ACCR/W0h Close loop acceleration when estimator is not yet fully aligned ( Hz / sec)
0h = 0.1 Hz/s
1h = 1 Hz/s
2h = 2 Hz/s
3h = 3 Hz/s
4h = 5 Hz/s
5h = 10 Hz/s
6h = 20 Hz/s
7h = 30 Hz/s
8h = 40 Hz/s
9h = 50 Hz/s
Ah = 100 Hz/s
Bh = 200 Hz/s
Ch = 500 Hz/s
Dh = 750 Hz/s
Eh = 1000 Hz/s
Fh = 2000 Hz/s
5-3ACTIVE_BRAKE_BUS_CURRENT_SLEW_RATER/W0h Bus Current slew rate during active braking (A/s)
0h = 10 A/s
1h = 50 A/s
2h = 100 A/s
3h = 250 A/s
4h = 500 A/s
5h = 1000 A/s
6h = 5000 A/s
7h = No Limit
2MPET_IPD_SELECTR/W0h Selection between MPET_IPD_CURRENT_LIMIT for IPD current limit, MPET_IPD_FREQ for IPD Repeat OR IPD_CURR_THR for IPD current limit, IPD_REPEAT for IPD Repeat
0h = Configured parameters for normal motor operation
1h = MPET specific parameters
1MPET_KE_MEAS_PARAMETER_SELECTR/W0h Selection between MPET_OPEN_LOOP_SLEW_RATE for slew rate, MPET_OPEN_LOOP_CURR_REF for current reference, MPET_OPEN_LOOP_SPEED_REF for speed reference OR OL_ACC_A1, OL_ACC_A2 for slew rate, open loop current reference for current reference and open to closed loop speed threshold for speed reference
0h = Configured parameters for normal motor operation
1h = MPET specific parameters
0IPD_HIGH_RESOLUTION_ENR/W0h IPD high resolution enable
0h = Disable
1h = Enable