JAJSNS6A december   2022  – april 2023 MCF8315A

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Characteristics of the SDA and SCL bus for Standard and Fast mode
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Output Stage
      2. 7.3.2  Device Interface
        1. 7.3.2.1 Interface - Control and Monitoring
        2. 7.3.2.2 I2C Interface
      3. 7.3.3  Step-Down Mixed-Mode Buck Regulator
        1. 7.3.3.1 Buck in Inductor Mode
        2. 7.3.3.2 Buck in Resistor mode
        3. 7.3.3.3 Buck Regulator with External LDO
        4. 7.3.3.4 AVDD Power Sequencing from Buck Regulator
        5. 7.3.3.5 Mixed Mode Buck Operation and Control
        6. 7.3.3.6 Buck Under Voltage Protection
        7. 7.3.3.7 Buck Over Current Protection
      4. 7.3.4  AVDD Linear Voltage Regulator
      5. 7.3.5  Charge Pump
      6. 7.3.6  Slew Rate Control
      7. 7.3.7  Cross Conduction (Dead Time)
      8. 7.3.8  Speed Control
        1. 7.3.8.1 Analog Mode Speed Control
        2. 7.3.8.2 PWM Mode Speed Control
        3. 7.3.8.3 I2C based Speed Control
        4. 7.3.8.4 Frequency Mode Speed Control
        5. 7.3.8.5 Speed Profiles
          1. 7.3.8.5.1 Linear Speed Profiles
          2. 7.3.8.5.2 Staircase Speed Profile
          3. 7.3.8.5.3 Forward-Reverse Speed Profile
      9. 7.3.9  Starting the Motor Under Different Initial Conditions
        1. 7.3.9.1 Case 1 – Motor is Stationary
        2. 7.3.9.2 Case 2 – Motor is Spinning in the Forward Direction
        3. 7.3.9.3 Case 3 – Motor is Spinning in the Reverse Direction
      10. 7.3.10 Motor Start Sequence (MSS)
        1. 7.3.10.1 Initial Speed Detect (ISD)
        2. 7.3.10.2 Motor Resynchronization
        3. 7.3.10.3 Reverse Drive
          1. 7.3.10.3.1 Reverse Drive Tuning
        4. 7.3.10.4 Motor Start-up
          1. 7.3.10.4.1 Align
          2. 7.3.10.4.2 Double Align
          3. 7.3.10.4.3 Initial Position Detection (IPD)
            1. 7.3.10.4.3.1 IPD Operation
            2. 7.3.10.4.3.2 IPD Release Mode
            3. 7.3.10.4.3.3 IPD Advance Angle
          4. 7.3.10.4.4 Slow First Cycle Startup
          5. 7.3.10.4.5 Open loop
          6. 7.3.10.4.6 Transition from Open to Closed Loop
      11. 7.3.11 Closed Loop Operation
        1. 7.3.11.1 Closed loop accelerate
        2. 7.3.11.2 Speed PI Control
        3. 7.3.11.3 Current PI Control
        4. 7.3.11.4 Overmodulation
      12. 7.3.12 Motor Parameters
        1. 7.3.12.1 Motor Resistance
        2. 7.3.12.2 Motor Inductance
        3. 7.3.12.3 Motor Back-EMF constant
      13. 7.3.13 Motor Parameter Extraction Tool (MPET)
      14. 7.3.14 Anti-Voltage Surge (AVS)
      15. 7.3.15 Output PWM Switching Frequency
      16. 7.3.16 Active Braking
      17. 7.3.17 PWM Modulation Schemes
      18. 7.3.18 Dead Time Compensation
      19. 7.3.19 Motor Stop Options
        1. 7.3.19.1 Coast (Hi-Z) Mode
        2. 7.3.19.2 Recirculation Mode
        3. 7.3.19.3 Low-Side Braking
        4. 7.3.19.4 High-Side Braking
        5. 7.3.19.5 Active Spin-Down
        6. 7.3.19.6 Align Braking
      20. 7.3.20 FG Configuration
        1. 7.3.20.1 FG Output Frequency
        2. 7.3.20.2 FG Open-Loop and Lock Behavior
      21. 7.3.21 DC Bus Current Limit
      22. 7.3.22 Protections
        1. 7.3.22.1  VM Supply Undervoltage Lockout
        2. 7.3.22.2  AVDD Undervoltage Lockout (AVDD_UV)
        3. 7.3.22.3  BUCK Undervoltage Lockout (BUCK_UV)
        4. 7.3.22.4  VCP Charge Pump Undervoltage Lockout (CPUV)
        5. 7.3.22.5  Overvoltage Protection (OVP)
        6. 7.3.22.6  Overcurrent Protection (OCP)
          1. 7.3.22.6.1 OCP Latched Shutdown (OCP_MODE = 00b)
          2. 7.3.22.6.2 OCP Automatic Retry (OCP_MODE = 01b)
          3. 7.3.22.6.3 OCP Report Only (OCP_MODE = 10b)
          4. 7.3.22.6.4 OCP Disabled (OCP_MODE = 11b)
        7. 7.3.22.7  Buck Overcurrent Protection
        8. 7.3.22.8  Hardware Lock Detection Current Limit (HW_LOCK_ILIMIT)
          1. 7.3.22.8.1 HW_LOCK_ILIMIT Latched Shutdown (HW_LOCK_ILIMIT_MODE = 00xxb)
          2. 7.3.22.8.2 HW_LOCK_ILIMIT Automatic recovery (HW_LOCK_ILIMIT_MODE = 01xxb)
          3. 7.3.22.8.3 HW_LOCK_ILIMIT Report Only (HW_LOCK_ILIMIT_MODE = 1000b)
          4. 7.3.22.8.4 HW_LOCK_ILIMIT Disabled (HW_LOCK_ILIMIT_MODE= 1xx1b)
        9. 7.3.22.9  Thermal Warning (OTW)
        10. 7.3.22.10 Thermal Shutdown (TSD)
        11. 7.3.22.11 Motor Lock (MTR_LCK)
          1. 7.3.22.11.1 MTR_LCK Latched Shutdown (MTR_LCK_MODE = 00xxb)
          2. 7.3.22.11.2 MTR_LCK Automatic Recovery (MTR_LCK_MODE= 01xxb)
          3. 7.3.22.11.3 MTR_LCK Report Only (MTR_LCK_MODE = 1000b)
          4. 7.3.22.11.4 MTR_LCK Disabled (MTR_LCK_MODE = 1xx1b)
        12. 7.3.22.12 Motor Lock Detection
          1. 7.3.22.12.1 Lock 1: Abnormal Speed (ABN_SPEED)
          2. 7.3.22.12.2 Lock 2: Abnormal BEMF (ABN_BEMF)
          3. 7.3.22.12.3 Lock3: No-Motor Fault (NO_MTR)
        13. 7.3.22.13 MPET Faults
        14. 7.3.22.14 IPD Faults
    4. 7.4 Device Functional Modes
      1. 7.4.1 Functional Modes
        1. 7.4.1.1 Sleep Mode
        2. 7.4.1.2 Standby Mode
        3. 7.4.1.3 Fault Reset (CLR_FLT)
    5. 7.5 External Interface
      1. 7.5.1 DRVOFF Functionality
      2. 7.5.2 DAC outputs
      3. 7.5.3 Current Sense Output
      4. 7.5.4 Oscillator Source
        1. 7.5.4.1 External Clock Source
      5. 7.5.5 External Watchdog
    6. 7.6 EEPROM access and I2C interface
      1. 7.6.1 EEPROM Access
        1. 7.6.1.1 EEPROM Write
        2. 7.6.1.2 EEPROM Read
      2. 7.6.2 I2C Serial Interface
        1. 7.6.2.1 I2C Data Word
        2. 7.6.2.2 I2C Write Transaction
        3. 7.6.2.3 I2C Read Transaction
        4. 7.6.2.4 I2C Communication Protocol Packet Examples
        5. 7.6.2.5 I2C Clock Stretching
        6. 7.6.2.6 CRC Byte Calculation
    7. 7.7 EEPROM (Non-Volatile) Register Map
      1. 7.7.1 Algorithm_Configuration Registers
      2. 7.7.2 Fault_Configuration Registers
      3. 7.7.3 Hardware_Configuration Registers
      4. 7.7.4 Internal_Algorithm_Configuration Registers
    8. 7.8 RAM (Volatile) Register Map
      1. 7.8.1 Fault_Status Registers
      2. 7.8.2 System_Status Registers
      3. 7.8.3 Device_Control Registers
      4. 7.8.4 Algorithm_Control Registers
      5. 7.8.5 Algorithm_Variables Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Speed Input before VM Power-up
      2. 8.2.2 Application Curves
        1. 8.2.2.1 Motor startup
        2. 8.2.2.2 MPET
        3. 8.2.2.3 Dead time compensation
        4. 8.2.2.4 Auto handoff
        5. 8.2.2.5 Motor stop – recirculation mode
        6. 8.2.2.6 Anti voltage surge (AVS)
        7. 8.2.2.7 Real time variable tracking using DACOUT
  10. 9 Power Supply Recommendations
    1. 9.1 Bulk Capacitance
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Thermal Considerations
      1. 10.3.1 Power Dissipation
  12. 11Device and Documentation Support
    1. 11.1 サポート・リソース
    2. 11.2 Trademarks
    3. 11.3 静電気放電に関する注意事項
    4. 11.4 用語集
  13. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.8.1 Fault_Status Registers

Table 7-45 lists the memory-mapped registers for the Fault_Status registers. All register offset addresses not listed in Table 7-45 should be considered as reserved locations and the register contents should not be modified.

Table 7-45 FAULT_STATUS Registers
OffsetAcronymRegister NameSection
E0hGATE_DRIVER_FAULT_STATUSFault Status RegisterGATE_DRIVER_FAULT_STATUS Register (Offset = E0h) [Reset = 00000000h]
E2hCONTROLLER_FAULT_STATUSFault Status RegisterCONTROLLER_FAULT_STATUS Register (Offset = E2h) [Reset = 00000000h]

Complex bit access types are encoded to fit into small table cells. Table 7-46 shows the codes that are used for access types in this section.

Table 7-46 Fault_Status Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Reset or Default Value
-nValue after reset or the default value

7.8.1.1 GATE_DRIVER_FAULT_STATUS Register (Offset = E0h) [Reset = 00000000h]

GATE_DRIVER_FAULT_STATUS is shown in Figure 7-83 and described in Table 7-47.

Return to the Summary Table.

Status of various gate driver faults

Figure 7-83 GATE_DRIVER_FAULT_STATUS Register
3130292827262524
DRIVER_FAULTBK_FLTRESERVEDOCPNPOROVPOTRESERVED
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
2322212019181716
OTWOTSOCP_HCOCP_LCOCP_HBOCP_LBOCP_HAOCP_LA
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
15141312111098
RESERVEDOTP_ERRBUCK_OCPBUCK_UVVCP_UVRESERVED
R-0hR-0hR-0hR-0hR-0hR-0h
76543210
RESERVED
R-0h
Table 7-47 GATE_DRIVER_FAULT_STATUS Register Field Descriptions
BitFieldTypeResetDescription
31DRIVER_FAULTR0h Logic OR of FAULT status registers. Mirrors nFAULT pin.
30BK_FLTR0h Buck Fault Bit
0h = No buck regulator fault condition is detected
1h = Buck regulator fault condition is detected
29RESERVEDR0h Reserved
28OCPR0h Over Current Protection Status Bit
0h = No overcurrent condition is detected
1h = Overcurrent condition is detected
27NPORR0h Supply Power On Reset Bit
0h = Power on reset condition is detected on VM
1h = No power-on-reset condition is detected on VM
26OVPR0h Supply Overvoltage Protection Status Bit
0h = No overvoltage condition is detected on VM
1h = Overvoltage condition is detected on VM
25OTR0h Overtemperature Fault Status Bit
0h = No overtemperature warning / shutdown is detected
1h = Overtemperature warning / shutdown is detected
24RESERVEDR0h Reserved
23OTWR0h Overtemperature Warning Status Bit
0h = No overtemperature warning is detected
1h = Overtemperature warning is detected
22OTSR0h Overtemperature Shutdown Status Bit
0h = No overtemperature shutdown is detected
1h = Overtemperature shutdown is detected
21OCP_HCR0h Overcurrent Status on High-side switch of OUTC
0h = No overcurrent detected on high-side switch of OUTC
1h = Overcurrent detected on high-side switch of OUTC
20OCP_LCR0h Overcurrent Status on Low-side switch of OUTC
0h = No overcurrent detected on low-side switch of OUTC
1h = Overcurrent detected on low-side switch of OUTC
19OCP_HBR0h Overcurrent Status on High-side switch of OUTB
0h = No overcurrent detected on high-side switch of OUTB
1h = Overcurrent detected on high-side switch of OUTB
18OCP_LBR0h Overcurrent Status on Low-side switch of OUTB
0h = No overcurrent detected on low-side switch of OUTB
1h = Overcurrent detected on low-side switch of OUTB
17OCP_HAR0h Overcurrent Status on High-side switch of OUTA
0h = No overcurrent detected on high-side switch of OUTA
1h = Overcurrent detected on high-side switch of OUTA
16OCP_LAR0h Overcurrent Status on Low-side switch of OUTA
0h = No overcurrent detected on low-side switch of OUTA
1h = Overcurrent detected on low-side switch of OUTA
15RESERVEDR0h Reserved
14OTP_ERRR0h OTP Error
0h = No OTP error is detected
1h = OTP Error is detected
13BUCK_OCPR0h Buck Regulator Overcurrent Status Bit
0h = No buck regulator overcurrent is detected
1h = Buck regulator overcurrent is detected
12BUCK_UVR0h Buck Regulator Undervoltage Status Bit
0h = No buck regulator undervoltage is detected
1h = Buck regulator undervoltage is detected
11VCP_UVR0h Charge Pump Undervoltage Status Bit
0h = No charge pump undervoltage is detected
1h = Charge pump undervoltage is detected
10-0RESERVEDR0h Reserved

7.8.1.2 CONTROLLER_FAULT_STATUS Register (Offset = E2h) [Reset = 00000000h]

CONTROLLER_FAULT_STATUS is shown in Figure 7-84 and described in Table 7-48.

Return to the Summary Table.

Status of various controller faults

Figure 7-84 CONTROLLER_FAULT_STATUS Register
3130292827262524
CONTROLLER_FAULTOTW_MCEIPD_FREQ_FAULTIPD_T1_FAULTIPD_T2_FAULTBUS_CURRENT_LIMIT_STATUSMPET_IPD_FAULTMPET_BEMF_FAULT
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
2322212019181716
ABN_SPEEDABN_BEMFNO_MTRMTR_LCKLOCK_LIMITHW_LOCK_LIMITMTR_UNDER_VOLTAGEMTR_OVER_VOLTAGE
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
15141312111098
SPEED_LOOP_SATURATIONCURRENT_LOOP_SATURATIONRESERVED
R-0hR-0hR-0h
76543210
RESERVEDWATCHDOG_FAULTSTL_ENABLE_STATUSSTL_STATUSAPP_RESET
R-0hR-0hR-0hR-0hR-0h
Table 7-48 CONTROLLER_FAULT_STATUS Register Field Descriptions
BitFieldTypeResetDescription
31CONTROLLER_FAULTR0h Logic OR of Controller FAULT status registers
30OTW_MCER0h Indicates overtemperature MCE
29IPD_FREQ_FAULTR0h Indicates IPD frequency fault
28IPD_T1_FAULTR0h Indicates IPD T1 fault
27IPD_T2_FAULTR0h Indicates IPD T2 fault
26BUS_CURRENT_LIMIT_STATUSR0h Indicates status of Bus Current limit
25MPET_IPD_FAULTR0h Indicates error during resistance and inductance measurement
24MPET_BEMF_FAULTR0h Indicates error during BEMF constant measurement
23ABN_SPEEDR0h Indicates Abnormal speed motor lock condition
22ABN_BEMFR0h Indicates Abnormal BEMF motor lock condition
21NO_MTRR0h Indicates No Motor fault
20MTR_LCKR0h Indicates when one of the motor lock is triggered
19LOCK_LIMITR0h Indicates Lock Ilimit fault
18HW_LOCK_LIMITR0h Indicates Hardware Lock Ilimit fault
17MTR_UNDER_VOLTAGER0h Indicates Motor Undervoltage fault
16MTR_OVER_VOLTAGER0h Indicates Motor Over voltage fault
15SPEED_LOOP_SATURATIONR0h Indicates speed loop saturation
14CURRENT_LOOP_SATURATIONR0h Indicates current loop saturation
13-4RESERVEDR0h Reserved
3WATCHDOG_FAULTR0h indicates Watchdog fault
2STL_ENABLE_STATUSR0h STL Enable Status
1STL_STATUSR0h STL Status
0APP_RESETR0h App Reset