JAJSSO4 December 2023 MCT8314Z
ADVANCE INFORMATION
After a motor lock event in this mode, all FETs are disabled and the nFAULT pin is driven low. The FAULT and MTR_LOCK bits are latched high in the SPI registers. Normal operation starts again (driver operation and the nFAULT pin is released) after clearing the faults through the CLR_FLT bit or an nSLEEP reset pulse (tRST).