5 Revision History

Changes from August 30, 2018 to December 10, 2019

• Changed the note that begins "Supply voltage changes faster than 0.2 V/µs can trigger a BOR reset..." in Section 8.3, Recommended Operating Conditions Go
• Added the note that begins "TI recommends that power to the DVCC pin must not exceed the limits..." in Section 8.3, Recommended Operating Conditions Go
• Added the note that begins "A capacitor tolerance of ±20% or better is required..." in Section 8.3, Recommended Operating Conditions Go
• Added the note "See MSP430 32-kHz Crystal Oscillators for details on crystal section, layout, and testing" to Section 8.12.3.1, XT1 Crystal Oscillator (Low Frequency) Go
• Changed the note that begins "Requires external capacitors at both terminals..." in Section 8.12.3.1, XT1 Crystal Oscillator (Low Frequency) Go
• Added the t_(int) parameter in Section 8.12.4.1, Digital Inputs Go
• Changed the parameter symbol from R_I to R_I,MUX in Section 8.12.8.1, ADC, Power Supply and Input Range Conditions Go
• Corrected the test conditions for the R_I,MUX parameter in Section 8.12.8.1, ADC, Power Supply and Input Range Conditions Go
• Added R_I,Misc TYP value of 34 kΩ in Section 8.12.8.1, ADC, Power Supply and Input Range Conditions Go
• Added t_CONVERT for external ADCCLK source in Section 8.12.8.2, ADC, 10-Bit Timing Parameters Go
• Added formula for R_I in Section 8.12.8.2, ADC, 10-Bit Timing Parameters Go
• Added the note that begins "t_Sample = ln(2ⁿ⁺¹) × τ ..." in Section 8.12.8.2, ADC, 10-Bit Timing Parameters Go
• Removed the description of "±3℃" in table note that starts "The device descriptor structure ..." of Section 8.12.8.3, ADC, 10-Bit Linearity Parameters Go
• Corrected bitfield from IRDSEL to IRDSSEL in Section 9.11.8, Timers (Timer0_B3), in the description that starts "The interconnection of Timer0_B3 ... " Go
• Corrected the ADCINCHx column heading in Table 9-14, ADC Channel Connections Go
• Added P1SELC information in Table 9-26, Port P1, P2 Registers (Base Address: 0200h) Go
• Added P2SELC information in Table 9-26, Port P1, P2 Registers (Base Address: 0200h) Go

Changes from July 14, 2017 to August 29, 2018

• Added note to V_SVSH- and V_SVSH+ parameters in Section 8.12.1.1, PMM, SVS and BOR Go
• Added the note "Controlled by the RTCCKSEL bit in the SYSCFG2 register" on Table 9-7, Clock Distribution Go
• Changed 1 µF capacitor to 10 µF in Figure 10-1, Power Supply Decoupling Go
• Updated text and figure in Section 11.2, Device Nomenclature Go

Changes from August 13, 2016 to July 13, 2017

• MSP430FR2100 および MSP430FR2000 デバイスを追加Go
• Section 1 「特長」の項目を再編成 Go
• ドキュメント全体で、RLL パッケージのパッケージ・ファミリを訂正 (QFN を VQFN に変更)Go
• 「Section 2」のアプリケーション一覧を更新Go
• Section 3「概要」を更新Go
• 図 4-1「機能ブロック図」で、ポート P1 のビット数を訂正 Go
• Updated the note that starts "This is the remapped functionality controlled by the TBRMP bit..." in Table 7-2, Signal Descriptions Go
• Updated the note that starts "This is the remapped functionality controlled by the USCIARMP bit..." in Table 7-2, Signal Descriptions Go
• Removed former Figure 5-2, Low-Power Mode 3 Supply Current vs Temperature Go
• Updated notes on Section 8.11, Thermal Resistance Characteristics Go
• Changed the entry for eUSCI_A in the LPM3 column from Off to Optional in Table 9-1, Operating Modes Go
• Updated the note that starts "This is the remapped functionality controlled by the USCIARMP bit..." in Table 9-11, eUSCI Pin Configurations Go
• Updated the note that starts "This is the remapped functionality controlled by the TBRMP bit..." in Table 9-12, Timer0_B3 Signal Connections Go
• Removed SYSBERRIV register (not supported) from Table 9-21, SYS Registers Go
• Updated descriptions of "Design Kits and Evaluation Modules" in Section 11.3, Tools and Software Go

Changes from August 11, 2016 to August 12, 2016

• ドキュメントのステータスを「製品プレビュー」から「量産データ」に変更Go