JAJSFD2A May   2018  – June 2018 OPA521

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      OPA521ブロック図
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Electrical Characteristics: Digital
    7. 6.7 Electrical Characteristics: Power Supply
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 IQSET Pin
      2. 7.3.2 EN Pin
      3. 7.3.3 ILIM Pin Current Limiting
      4. 7.3.4 IFLAG and TFLAG Pins
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Interfacing the OPA521 to the AC Mains
          1. 8.2.2.1.1 Low-Voltage Capacitor
          2. 8.2.2.1.2 High-Voltage Capacitor
          3. 8.2.2.1.3 Inductor
          4. 8.2.2.1.4 Line Coupling Transformer
        2. 8.2.2.2 Circuit Protection
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Thermal Considerations
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 デバイス・サポート
      1. 11.1.1 デベロッパー・ネットワークの製品に関する免責事項
    2. 11.2 ドキュメントのサポート
      1. 11.2.1 関連資料
    3. 11.3 ドキュメントの更新通知を受け取る方法
    4. 11.4 コミュニティ・リソース
    5. 11.5 商標
    6. 11.6 静電気放電に関する注意事項
    7. 11.7 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.6 Electrical Characteristics: Digital

At TCASE = 25°C, V+ = 15 V, IN+ = (V+) / 2, RLOAD = 50 Ω unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DIGITAL INPUTS (ENABLE, IQSET)
Leakage input current GND ≤ VIN ≤ 3.3 –1 0.01 1 µA
VIH High-level input voltage 2 3.3 V
VIL Low-level input voltage GND 0.8 V
EN pin function (active high) EN pin high 2 < EN < 3.3 Device in normal operation
EN pin low EN < 0.8 Device in shutdown
IQSET pin function (active high) IQSET pin high IQSET > 2 Device in FCC/ARIB mode (IQ = 78 mA (typ))
IQSET pin low IQSET < 0.8 Device in CENELEC mode (IQ = 51 mA (typ))
DIGITAL OUTPUTS (TFLAG, IFLAG)
IOH High-level output current VOH = 3.3 V 1 µA
VOL Low-level output voltage IOL = 4 mA 0.4 V
IOL Low-level output current VOL = 400 mV 4 mA
TFLAG (active high, open-drain) TFLAG pin high TFLAG sink high < 1 µA Device is in thermal shutdown
TFLAG pin low TFLAG < 0.4 V Device is not in thermal shutdown
IFLAG (active high, open-drain) IFLAG pin high IFLAG sink high < 1 µA Device is in current limit
IFLAG pin low IFLAG < 0.4 V Device is not in current limit
SHUTDOWN MODE TIMING
Enable time SD pin transitions from low to high 3 ms
Disable time SD pin transitions from high to low 2 ms