SLASE63 November   2014 PCM5252

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Device Comparison
  6. Pin Configuration and Functions
    1. 6.1 Control Mode Effect On Pin Assignments
    2. 6.2 Pin Assignments
  7. Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Switching Characteristics
    7. 7.7  Timing Requirements: SCK Input
    8. 7.8  Timing Requirements: PCM Audio Data
    9. 7.9  Timing Requirements: I2S Master, See
    10. 7.10 Timing Requirements: XSMT
    11. 7.11 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Terminology
      2. 8.3.2 Audio Data Interface
        1. 8.3.2.1 Audio Serial Interface
        2. 8.3.2.2 PCM Audio Data Formats
        3. 8.3.2.3 Zero Data Detect
      3. 8.3.3 XSMT Pin (Soft Mute / Soft Un-Mute)
      4. 8.3.4 Audio Processing
        1. 8.3.4.1  PCM5252 Audio Processing Options
          1. 8.3.4.1.1 Overview
          2. 8.3.4.1.2 miniDSP Instruction Register
          3. 8.3.4.1.3 Digital Output
          4. 8.3.4.1.4 Software
        2. 8.3.4.2  Interpolation Filter
        3. 8.3.4.3  Overview
        4. 8.3.4.4  Smart SOA
        5. 8.3.4.5  Smart BASS
        6. 8.3.4.6  Smart Protection
        7. 8.3.4.7  Implementing a Real World Design
        8. 8.3.4.8  Digital Output
        9. 8.3.4.9  Software
        10. 8.3.4.10 Process Flow
      5. 8.3.5 DAC and Differential Analog Outputs
        1. 8.3.5.1 Analog Outputs
        2. 8.3.5.2 Choosing Between VREF and VCOM Modes
          1. 8.3.5.2.1 Voltage Reference and Output Levels
          2. 8.3.5.2.2 Mode Switching Sequence, from VREF Mode to VCOM Mode
        3. 8.3.5.3 Digital Volume Control
          1. 8.3.5.3.1 Emergency Ramp-Down
        4. 8.3.5.4 Analog Gain Control
      6. 8.3.6 Reset and System Clock Functions
        1. 8.3.6.1 Clocking Overview
        2. 8.3.6.2 Clock Slave Mode With Master and System Clock (SCK) Input (4 Wire I2S)
        3. 8.3.6.3 Clock Slave Mode With BCK PLL to Generate Internal Clocks (3-Wire PCM)
        4. 8.3.6.4 Clock Generation Using the PLL
        5. 8.3.6.5 PLL Calculation
          1. 8.3.6.5.1 Examples:
            1. 8.3.6.5.1.1 Recommended PLL Settings
        6. 8.3.6.6 Clock Master Mode from Audio Rate Master Clock
        7. 8.3.6.7 Clock Master from a Non-Audio Rate Master Clock
    4. 8.4 Device Functional Modes
      1. 8.4.1 Choosing a Control Mode
        1. 8.4.1.1 Software Control
          1. 8.4.1.1.1 SPI Interface
            1. 8.4.1.1.1.1 Register Read and Write Operation
          2. 8.4.1.1.2 I2C Interface
            1. 8.4.1.1.2.1 Slave Address
            2. 8.4.1.1.2.2 Register Address Auto-Increment Mode
            3. 8.4.1.1.2.3 Packet Protocol
            4. 8.4.1.1.2.4 Write Register
            5. 8.4.1.1.2.5 Read Register
            6. 8.4.1.1.2.6 Timing Characteristics
      2. 8.4.2 VREF and VCOM Modes
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 High Fidelity Smartphone Application
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Initialization Script
        3. 9.2.1.3 Application Performance Plot
  10. 10Power Supply Recommendations
    1. 10.1 Power Supply Distribution and Requirements
    2. 10.2 Recommended Powerdown Sequence
      1. 10.2.1 XSMT = 0
      2. 10.2.2 Clock Error Detect
      3. 10.2.3 Planned Shutdown
      4. 10.2.4 Unplanned Shutdown
    3. 10.3 External Power Sense Undervoltage Protection Mode
    4. 10.4 Power-On Reset Function
      1. 10.4.1 Power-On Reset, DVDD 3.3-V Supply
      2. 10.4.2 Power-On Reset, DVDD 1.8-V Supply
    5. 10.5 PCM5252 Power Modes
      1. 10.5.1 Setting Digital Power Supplies and I/O Voltage Rails
        1. 13.2.2 PLL Tables for Software Controlled Devices
      2. 10.5.2 Power Save Modes
        1. 13.2.1.3 Page 1 Registers
          1. 13.2.1.3.1 Page 1 / Register 1
          2. 13.2.1.3.2 Page 1 / Register 2
          3. 13.2.1.3.3 Page 1 / Register 5
          4. 13.2.1.3.4 Page 1 / Register 6
          5. 13.2.1.3.5 Page 1 / Register 7
          6. 13.2.1.3.6 Page 1 / Register 8
          7. 13.2.1.3.7 Page 1 / Register 9
        2. 13.2.1.4 Page 44 Registers
          1. 13.2.1.4.1 Page 44 / Register 1
        3. 13.2.1.5 Page 253 Registers
          1. 13.2.1.5.1 Page 253 / Register 63
          2. 13.2.1.5.2 Page 253 / Register 64
      3. 10.5.3 Power Save Parameter Programming
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 13.2.1.2.19 Page 0 / Register 24
      2. 13.2.1.2.20 Page 0 / Register 27
      3. 13.2.1.2.21 Page 0 / Register 28
      4. 13.2.1.2.22 Page 0 / Register 29
      5. 13.2.1.2.23 Page 0 / Register 30
      6. 13.2.1.2.24 Page 0 / Register 32
      7. 13.2.1.2.25 Page 0 / Register 33
      8. 13.2.1.2.26 Page 0 / Register 34
      9. 13.2.1.2.27 Page 0 / Register 35
      10. 13.2.1.2.28 Page 0 / Register 36
      11. 13.2.1.2.29 Page 0 / Register 37
      12. 13.2.1.2.30 Page 0 / Register 40
      13. 13.2.1.2.31 Page 0 / Register 41
      14. 13.2.1.2.32 Page 0 / Register 42
      15. 13.2.1.2.33 Page 0 / Register 43
      16. 13.2.1.2.34 Page 0 / Register 44
      17. 13.2.1.2.35 Page 0 / Register 59
      18. 13.2.1.2.36 Page 0 / Register 60
      19. 13.2.1.2.37 Page 0 / Register 61
      20. 13.2.1.2.38 Page 0 / Register 62
      21. 13.2.1.2.39 Page 0 / Register 63
      22. 13.2.1.2.40 Page 0 / Register 64
      23. 13.2.1.2.41 Page 0 / Register 65
      24. 13.2.1.2.42 Page 0 / Register 80
      25. 13.2.1.2.43 Page 0 / Register 81
      26. 13.2.1.2.44 Page 0 / Register 82
      27. 13.2.1.2.45 Page 0 / Register 83
      28. 13.2.1.2.46 Page 0 / Register 84
      29. 13.2.1.2.47 Page 0 / Register 85
      30. 13.2.1.2.48 Page 0 / Register 86
      31. 13.2.1.2.49 Page 0 / Register 87
      32. 13.2.1.2.50 Page 0 / Register 90
      33. 13.2.1.2.51 Page 0 / Register 91
      34. 13.2.1.2.52 Page 0 / Register 92
      35. 13.2.1.2.53 Page 0 / Register 93
      36. 13.2.1.2.54 Page 0 / Register 94
      37. 13.2.1.2.55 Page 0 / Register 95
      38. 13.2.1.2.56 Page 0 / Register 108
      39. 13.2.1.2.57 Page 0 / Register 109
      40. 13.2.1.2.58 Page 0 / Register 114
      41. 13.2.1.2.59 Page 0 / Register 115
      42. 13.2.1.2.60 Page 0 / Register 118
      43. 13.2.1.2.61 Page 0 / Register 119
      44. 13.2.1.2.62 Page 0 / Register 120
      45. 13.2.1.2.63 Page 0 / Register 121
      46. 13.2.1.2.64 Page 0 / Register 122
      47. 13.2.1.2.65 Page 0 / Register 123
      48. 13.2.1.2.66 Page 0 / Register 124
      49. 13.2.1.2.67 Page 0 / Register 125
    2. 11.2 Layout Example
  12. 12Programming
    1. 12.1 Coefficient Data Formats
    2. 12.2 Power Down and Reset Behavior
  13. 13Register Maps
    1. 13.1 PCM5252 Register Map
      1. 13.1.1 Detailed Register Descriptions
        1. 13.1.1.1 Register Map Summary
        2. 13.1.1.2 Page 0 Registers
        3. 13.1.1.3 Page 1 Registers
        4. 13.1.1.4 Page 44 Registers
        5. 13.1.1.5 Page 253 Registers
      2. 13.1.2 PLL Tables for Software Controlled Devices
  14. 14Device and Documentation Support
    1. 14.1 Community Resources
    2. 14.2 Trademarks
    3. 14.3 Electrostatic Discharge Caution
  15. 15Mechanical, Packaging, and Orderable Information
  16. 14Device and Documentation Support
    1. 14.1 Community Resources
    2. 14.2 Trademarks
    3. 14.3 Electrostatic Discharge Caution
  17. 15Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Detailed Description

Overview

The PCM5252 PurePath™ Smart Amp enhances the bass, sound fidelity and increased loudness by driving the speaker to its thermal and mechanical limits.

TI's PurePath™ Smart Amp technology allows speakers to be driven with more peak power than their average-power rating, without damage to the speaker by voice coil over excursion or thermal overload.

Sophisticated speaker models (electro-mechanical-thermal) are used as a foundation for the protection and enhancement of the system. This is done by modeling the loudspeaker in the on-chip miniDSP and running an adaptive algorithm that modifies the output based on the modeled conditions of the speaker.

TI provides a PurePath™ Console (PPC) GUI, including a TI learning board that measures the loudspeaker parameters. The PPC GUI generates the code for download to the device on boot-up.

Smart Amp technology in the PCM5252 devices use information from the SOA (Safe Operating Area) characterization details for the loudspeaker, as well as real-world temperature, and uses this data in an adaptive control algorithm in order to control Smart Bass and Smart DRP (Dynamic Range Preservation). The protection side of the algorithm is also used for thermal protection and mechanical voice coil excursion protection.

The integrated PLL on the device provided adds the flexibility to remove the system clock (commonly known as master clock), allowing a 3-wire I2S connection and reducing system EMI. In addition, the PLL is completely programmable, allowing the device to become the I2S clock master and drive a DSP serial port as a slave. The PLL also accepts a non-standard clock (up to 50 MHz) as a source to generate the audio related clock (for example, 24.576 MHz).

Powersense undervoltage protection utilizes a two-level mute system. Upon clock error or system power failure, the device digitally attenuates the data (or last known good data) and then mutes the analog circuit.

Compared with existing DAC technology, the PCM5252 devices offer up to 20 dB of lower out-of-band noise, reducing EMI and aliasing in downstream amplifiers/ADCs (from traditional 100-kHz OBN measurements to
3 MHz).

The PCM5252 devices accept industry-standard audio data formats with 16-bit to 32-bit data. Sample rates up to 384 kHz are supported.

Functional Block Diagram

PCM5252 fbd_pcm5252_slase63.gif

Feature Description

Terminology

Control registers in this data sheet are given by REGISTER BIT/BYTE NAME (Page.x HEX ADDRESS). SE refers to single-ended analog inputs, DIFF refers to Differential analog inputs. SCK (System Clock) and MCLK (Master Clock) are used interchangeably. Sampling frequency is symbolized by fS. Full scale is symbolized by FS. Sample time as a unit is symbolized by tS.

Audio Data Interface

Audio Serial Interface

The audio interface port is a 3-wire serial port with the signals LRCK, BCK, and DIN. BCK is the serial audio bit clock, used to clock the serial data present on DIN into the serial shift register of the audio interface. Serial data is clocked into the PCM5252 on the rising edge of BCK. LRCK is the serial audio left/right word clock. LRCK polarity for left/right is given by the format selected.

Table 4. PCM5252 Audio Data Formats, Bit Depths and Clock Rates

CONTROL MODE FORMAT DATA BITS MAX LRCK FREQUENCY [fS] SCK RATE [x fS] BCK RATE [x fS]
Software Control
(SPI or I2S)
I2S/LJ 32, 24, 20, 16 Up to 192 kHz 128 – 3072 64, 48, 32
384 kHz 64, 128 64, 48, 32
TDM/DSP 32, 24, 20, 16 Up to 48 kHz 128 – 3072 128, 256
96 kHz 128 – 512 128, 256
192 kHz 128, 192, 256 128
Hardware Control I2S/LJ 32, 24, 20, 16 Up to 192 kHz 128 – 3072 64, 48, 32
384 kHz 64, 128 64, 48, 32

The PCM5252 requires the synchronization of LRCK and system clock, but does not need a specific phase relation between LRCK and system clock.

If the relationship between LRCK and system clock changes more than ±5 SCK, internal operation (using an onchip oscillator) is initialized within one sample period and analog outputs are forced to the bipolar zero level until resynchronization between LRCK and system clock is completed.

If the relationship between LRCK and BCK are invalid more than 4 LRCK periods, internal operation (using an onchip oscillator) is initialized within one sample period and analog outputs are forced to the bipolar zero level until resynchronization between LRCK and BCK is completed.

PCM Audio Data Formats

The PCM5252 supports industry-standard audio data formats, including standard I2S and left-justified. Data formats are selected via Register (Pg0Reg40). All formats require binary twos-complement, MSB-first audio data; up to 32-bit audio data is accepted.

The PCM5252 also supports right-justified and TDM/DSP in software control mode. I2S, LJ, RJ, and TDM/DSP are selected using Register (Pg0Reg40). All formats require binary twos-complement, MSB-first audio data. Up to 32 bits are accepted. Default setting is I2S and 24-bit word length.

PCM5252 f_pcm51xx_aud_data_format_lj.gif Figure 18. Left-Justified Audio Data Format
PCM5252 f_pcm51xx_aud_data_format_i2s.gif
I2S Data Format; L-channel = LOW, R-channel = HIGH
Figure 19. I2S Audio Data Format

NOTE

In TDM Modes, Duty Cycle of LRCK should be 1x BCK at minimum. Rising edge is considered frame start.

PCM5252 f_pcm51xx_aud_data_format_tdm2.gif
TDM/DSP Data Format; L-channel = FIRST, R-channel = LAST with OFFSET = 1
Figure 20. TDM/DSP 2 Audio Data Format
PCM5252 f_pcm51xx_aud_data_format_tdm3.gif
TDM/DSP Data Format; L-channel = FIRST, R-channel = LAST with OFFSET = N
Figure 21. TDM/DSP 3 Audio Data Format

Zero Data Detect

The PCM5252 has a zero-detect function. When the device detects the continuous zero data for both left and right channels, or separate channels, Analog mutes are set to both OUTL and OUTR, or separate OUTL and OUTR. These are controlled by Page 0, Register 65, D(2:1) as shown in Table 5.

Table 5. Zero Data Detection Mode

ATMUTECTL VALUE FUNCTION
Bit : 2 0 Independently L-ch or R-ch are zero data for zero data detection
1 (Default) Both L-ch and R-ch have to be zero data for zero data detection
Bit : 1 0 Zero detection and analog mute are disabled for R-ch
1 (Default) Zero detection analog mute are enabled for R-ch
Bit : 0 0 Zero detection analog mute are disabled for L-ch
1 (Default) Zero detection analog mute are enabled for L-ch

Table 6. Zero Data Detection Time

ATMUTETIML / ATMUTETIMR NUMBER OF LRCKs TIME AT 48 kHz
0 0 0 1024 21 ms
0 0 1 5120 106 ms
0 1 0 10240 213 ms
0 1 1 25600 533 ms
1 0 0 51200 1.066 sec
1 0 1 102400 2.133 sec
1 1 0 256000 5.333 sec
1 1 1 512000 10.66 sec

XSMT Pin (Soft Mute / Soft Un-Mute)

An external digital host controls the PCM5252 soft mute function by driving the XSMT pin with a specific minimum rise time (tr) and fall time (tf) for soft mute and soft un-mute. The PCM5252 requires tr and tf times of less than 20 ns. In the majority of applications, this is no problem; however, traces with high capacitance may have issues.

When the XSMT pin is shifted from high to low (3.3 V to 0 V), a soft digital attenuation ramp begins. –1-dB attenuation is then applied every sample time from 0 dBFS to –∞. The soft attenuation ramp takes 104 samples.

When the XSMT pin is shifted from low to high (0 V to 3.3 V), a soft digital un-mute is started. 1-dB gain steps are applied every sample time from –∞ to 0 dBFS. The un-mute takes 104 samples.

In systems where XSMT is not required, it can be directly connected to AVDD.

Audio Processing

PCM5252 Audio Processing Options

Overview

The PCM5252 features a programmable miniDSP core that offers Hybrid-Flows which are a RAM/ROM combination of code. Common functions are embedded in ROM, and custom RAM flows, created by TI can be run on the miniDSP core. The algorithms for the miniDSP must be loaded into the device after power up. The miniDSP can run up to 1024 instructions on every audio sample at a 48kHz sample rate. Development is done using Purepath™ Console software.

NOTE

At higher sampling frequencies, fewer instruction cycles are available. (For example, 512 instructions can be done in a 96-kHz frame.)

The PCM5252 supports two different code sources. ROM based process flow (See the next section for how to select) and RAM based process flow. In program 31 (RAM based), different algorithms can be called from ROM - such as EQ, DRC and Zero Crossing volume control. Please see the PurePath Studio Development Environment for more details.

Smart Amplifier is another process flow that is available for use. Program 5 integrates a 2.1 Smart Amplifier system, without Smart Bass enhancement. A mixed RAM/ROM Mode is available using program 31 that can do a 2.0 Stereo Smart Amplifier with Smart Bass enhancement. However, the MIPS requirements for Smart Amplifier allow the process flow to work up to 48kHz sampling rate. Any higher sampling rates will require a custom process flow with limited processing (such as a simpler EQ and Dynamic Range Control),

miniDSP Instruction Register

Registers on Page 152-169 are 25-bit instructions for the miniDSP engine. For details, see Table 43. 7 bits of Instr(32:25) in Base register +0 are reserved bits. 1 bit of Instr(24) - (LSB) in Base register +0 is MSB bit of 25 bit instruction. These instructions control miniDSP operation. When the fully programmable miniDSP mode is enabled and the DAC channel is powered up, the read and write access to these registers is disabled.

Digital Output

The PCM5252 supports an SDOUT output. This can be selected within the process flow, and driven out of a GPIO pin selected in the register map (for example, Page 0 / Register 80). Users should note that the I2S output will be attenuated by 0.5 dB. A full scale (FS) output will actually be FS-0.5dB. This can be compensated for within the process flow using PurePath Studio. The I2S output can be a separate audio stream to the analog DAC output, allowing 2.1 and 2.2 systems to be implimented. By default, the SDOUT is not linked to the volume control registers on Page 0 / Register 60, 61, 62. However, it is possible to configure the SDOUT component in Purepath studio to mirror that register.

Software

Software development for the PCM5252 is supported through TI's comprehensive PurePath Console; a powerful, easy-to-use tool designed specifically to simplify software development on the PCM5252 miniDSP audio platform. The Graphical Development Environment consists of number of Hybrid Flows that can be downloaded to the device and run on the miniDSP.

Please visit the PCM5252 product folder on www.ti.com to learn more about PurePath Console and the latest status on available, ready-to-use DSP algorithms.

Interpolation Filter

The PCM5252 provides 4 types of interpolation filters, selectable by writing to Page 0, Register 43, D(4:0).

Additional RAM based Hybrid Flows can be implemented by selecting Program 31, and downloading instructions and coefficients to the device.

Table 7. ROM Preset Programs

PROGRAM NUMBER D(4:0) DESCRIPTION MINIMUM CYCLES
0 0 0000 Reserved
1 0 0001 Normal x8/x4/x2/x1 Interpolation Filter(1) 256
2 0 0010 Low Latency x8/x4/x2/x1 Interpolation Filter(1) 256
3 0 0011 High Attenuation x8/x4/x2 Interpolation Filter(1) 512
4 0 0100 Reserved
5 0 0101 Reserved
6 0 0110 Reserved
7 0 0111 Asymmetric FIR Interpolation Filter(1) 512
: : Reserved
31 1 1111 RAM Process flow (e.g. can be used to implement Smart Amplifier 2.1 Mode)
At fs=44.1 kHz, de-emphasis filter is supported.

The PCM5252 supports four sampling modes (single rate, dual rate, quad rate, and octal rate) which produce different oversampling rates (OSR) in the interpolation digital filter operation. These are shown in Table 8.

Table 8. Sampling Modes and Oversampling Rates

SAMPLING MODE SAMPLING FREQUENCY (fS) kHz OVERSAMPLING RATE (OSR)
Single Rate 8 8 or 16
16
32
44.1
48
Dual Rate 88.2 4
96
Quad Rate 176.4 2
192
Octal Rate 384 1 (Bypass)

Table 9. Normal x8 Interpolation Filter, Single Rate

PARAMETER CONDITION VALUE (TYP) VALUE (MAX) UNIT
Filter Gain Pass Band 0 ……. 0.45 × fS ±0.01 dB
Filter Gain Stop Band 0.55 × fS ….. 7.455 × fS –60 dB
Filter Group Delay 20 / fs S

SPACE

PCM5252 G012_gphpcm51xx_frequency_response_x8_normal.gif Figure 22. Normal x8 Interpolation Filter
Frequency Response
PCM5252 G034_gphpcm51xx_pass_band_ripple_x8_normal.gif Figure 24. Normal x8 Interpolation Filter Passband Ripple
PCM5252 G023_gphpcm51xx_impulse_response_x8_normal.gif Figure 23. Normal x8 Interpolation Filter
Impulse Response

Table 10. Normal x4 Interpolation Filter, Dual Rate

PARAMETER CONDITION VALUE (TYP) VALUE (MAX) UNIT
Filter Gain Pass Band 0 ……. 0.45 × fS ±0.01 dB
Filter Gain Stop Band 0.55 × fS ….. 3.455 × fS –60 dB
Filter Group Delay 20 / fs S

SPACE

PCM5252 G009_gphpcm51xx_frequency_response_x4_slase12.gif Figure 25. Normal x4 Interpolation Filter
Frequency Response
PCM5252 G031_gphpcm51xx_pass_band_ripple_x4_normal_slase12.gif Figure 27. Normal x4 Interpolation Filter Passband Ripple
PCM5252 G020_gphpcm51xx_impulse_response_x4_normal.gif Figure 26. Normal x4 Interpolation Filter
Impulse Response

Table 11. Normal x2 Interpolation Filter, Quad Rate

PARAMETER CONDITION VALUE (TYP) VALUE (MAX) UNIT
Filter Gain Pass Band 0 ……. 0.45 × fS ±0.01 dB
Filter Gain Stop Band 0.55 × fS ….. 1.455 × fS –60 dB
Filter Group Delay 20 / fs S

SPACE

PCM5252 G006_gphpcm51xx_frequency_response_x4_slase12.gif Figure 28. Normal x2 Interpolation Filter
Frequency Response
PCM5252 G028_gphpcm51xx_pass_band_ripple_x2_normal_slase12.gif Figure 30. Normal x2 Interpolation Filter Passband Ripple
PCM5252 G017_gphpcm51xx_impulse_response_x2_normal.gif Figure 29. Normal x2 Interpolation Filter
Impulse Response

Table 12. Low Latency x8 Interpolation Filter, Single Rate

PARAMETER CONDITION VALUE (TYP) VALUE (MAX) UNIT
Filter Gain Pass Band 0 ……. 0.45 × fS ±0.001 dB
Filter Gain Stop Band 0.55 × fS ….. 7.455 × fS –52 dB
Filter Group Delay 3.5 × ts S

SPACE

PCM5252 G011_gphpcm51xx_frequency_response_x8_lowlt.gif Figure 31. Low Latency x8 Interpolation Filter
Frequency Response
PCM5252 G033_gphpcm51xx_pass_band_ripple_x8_lowlt.gif Figure 33. Low Latency x8 Interpolation Filter Passband Ripple
PCM5252 G022_gphpcm51xx_impulse_response_x8_lowlt.gif Figure 32. Low Latency x8 Interpolation Filter
Impulse Response

Table 13. Low Latency x4 Interpolation Filter, Dual Rate

PARAMETER CONDITION VALUE (TYP) VALUE (MAX) UNIT
Filter Gain Pass Band 0 ……. 0.45 × fS ±0.001 dB
Filter Gain Stop Band 0.55 × fS ….. 3.455 × fS –52 dB
Filter Group Delay 3.5 × ts S

SPACE

PCM5252 G008_gphpcm51xx_frequency_response_x4_slase12.gif Figure 34. Low Latency x4 Interpolation Filter
Frequency Response
PCM5252 G030_gphpcm51xx_pass_band_ripple_x4_lowlt_slase12.gif Figure 36. Low Latency x4 Interpolation Filter Passband Ripple
PCM5252 G019_gphpcm51xx_impulse_response_x4_lowlt.gif Figure 35. Low Latency x4 Interpolation Filter
Impulse Response

Table 14. Low Latency ×2 Interpolation Filter, Quad Rate

PARAMETER CONDITION VALUE (TYP) VALUE (MAX) UNIT
Filter Gain Pass Band 0 ……. 0.45 × fS ±0.001 dB
Filter Gain Stop Band 0.55 × fS ….. 1.455 × fS –52 dB
Filter Group Delay 3.5 × ts S

SPACE

PCM5252 G005_gphpcm51xx_frequency_response_x4_slase12.gif Figure 37. Low Latency x2 Interpolation Filter
Frequency Response
PCM5252 G030_gphpcm51xx_pass_band_ripple_x4_lowlt_slase12.gif Figure 39. Low Latency x2 Interpolation Filter Passband Ripple
PCM5252 G016_gphpcm51xx_impulse_response_x2_lowlt.gif Figure 38. Low Latency x2 Interpolation Filter
Impulse Response

Table 15. Asymmetric FIR x8 Interpolation Filter, Single Rate

PARAMETER CONDITION VALUE (TYP) VALUE (MAX) UNIT
Filter Gain Pass Band 0 ……. 0.40 × fS ±0.05 dB
Filter Gain Stop Band 0.72 × fS ….. 7.28 × fS –50 dB
Filter Group Delay 1.2 × ts S

SPACE

PCM5252 gphpcm51xx_frequency_response_x8_asymFIR.png Figure 40. Asymmetric FIR x8 Interpolation Filter Frequency Response, Single Rate
PCM5252 gphpcm51xx_pass_band_ripple_x8_asymFIR.png Figure 42. Asymmetric FIR x8 Interpolation Filter Passband Ripple, Single Rate
PCM5252 gphpcm51xx_impulse_response_x8_asymFIR.png Figure 41. Asymmetric FIR x8 Interpolation Filter Impulse Response, Single Rate

Table 16. Asymmetric FIR x4 Interpolation Filter, Dual Rate

PARAMETER CONDITION VALUE (TYP) VALUE (MAX) UNIT
Filter Gain Pass Band 0 ……. 0.40 × fS ±0.05 dB
Filter Gain Stop Band 0.72 × fS ….. 3.28 × fS –50 dB
Filter Group Delay 1.2 × ts S

SPACE

PCM5252 G002_gphpcm51xx_frequency_response_x4_asymFIR_slase12.gif Figure 43. Asymmetric FIR x4 Interpolation Filter Frequency Response, Dual Rate
PCM5252 gphpcm51xx_pass_band_ripple_x4_asymFIR.png Figure 45. Asymmetric x4 Interpolation Filter Passband Ripple, Dual Rate
PCM5252 gphpcm51xx_impulse_response_x4_asymFIR.png Figure 44. Asymmetric FIR x4 Interpolation Filter Impulse Response, Dual Rate

Table 17. Asymmetric FIR x2 Interpolation Filter, Quad Rate

PARAMETER CONDITION VALUE (TYP) VALUE (MAX) UNIT
Filter Gain Pass Band 0 ……. 0.40 × fS ±0.05 dB
Filter Gain Stop Band 0.72 × fS ….. 1.28 × fS –50 dB
Filter Group Delay 1.2 × ts S

SPACE

PCM5252 G001_gphpcm51xx_frequency_response_x2_asymFIR_slase12.gif Figure 46. Asymmetric FIR x2 Interpolation Filter Frequency Response, Quad Rate
PCM5252 G100_gphpcm51xx_pass_band_ripple_x2_asymFIR_slase12.gif Figure 48. Asymmetric x2 Interpolation Filter Passband Ripple, Quad Rate
PCM5252 gphpcm51xx_impulse_response_x2_asymFIR.png Figure 47. Asymmetric FIR x2 Interpolation Filter Impulse Response, Quad Rate

Table 18. High-Attentuation x8 Interpolation Filter, Single Rate

PARAMETER CONDITION VALUE (TYP) VALUE (MAX) UNIT
Filter Gain Pass Band 0 ……. 0.45 × fS ±0.0005 dB
Filter Gain Stop Band 0.55 × fS ….. 7.455 × fS –100 dB
Filter Group Delay 33.7 × tS S

SPACE

PCM5252 gphpcm51xx_frequency_response_x8_high_ATT.png Figure 49. High-Attentuation x8 Interpolation Filter Frequency Response, Single Rate
PCM5252 gphpcm51xx_pass_band_ripple_x8_high_ATT.png Figure 51. High-Attentuation x8 Interpolation Filter Passband Ripple, Single Rate
PCM5252 gphpcm51xx_impulse_response_x8_high_ATT.png Figure 50. High-Attentuation x8 Interpolation Filter Impulse Response, Single Rate

Table 19. High-Attentuation x4 Interpolation Filter, Dual Rate

PARAMETER CONDITION VALUE (TYP) VALUE (MAX) UNIT
Filter Gain Pass Band 0 ……. 0.45 × fS ±0.0005 dB
Filter Gain Stop Band 0.55 × fS ….. 3.455 × fS –100 dB
Filter Group Delay 33.7 × tS S

SPACE

PCM5252 G004_gphpcm51xx_frequency_response_x4_high_ATT_slase12.gif Figure 52. High-Attentuation x4 Interpolation Filter Frequency Response, Dual Rate
PCM5252 G101_gphpcm51xx_pass_band_ripple_x4_high_ATT_slase12.gif Figure 54. High-Attentuation x4 Interpolation Filter Passband Ripple, Dual Rate
PCM5252 gphpcm51xx_impulse_response_x4_high_ATT.png Figure 53. High-Attentuation x4 Interpolation Filter Impulse Response, Dual Rate

Table 20. High-Attentuation x2 Interpolation Filter, Quad Rate

PARAMETER CONDITION VALUE (TYP) VALUE (MAX) UNIT
Filter Gain Pass Band 0 ……. 0.45 × fS ±0.0005 dB
Filter Gain Stop Band 0.55 × fS ….. 1.455 × fS –100 dB
Filter Group Delay 33.7 × tS S

SPACE

PCM5252 G003_gphpcm51xx_frequency_response_x2_high_ATT_slase12.gif Figure 55. High-Attentuation x2 Interpolation Filter Frequency Response, Quad Rate
PCM5252 G102_gphpcm51xx_pass_band_ripple_x2_high_ATT_slase12.gif Figure 57. High-Attentuation x2 Interpolation Filter Passband Ripple, Quad Rate
PCM5252 gphpcm51xx_impulse_response_x2_high_ATT.png Figure 56. High-Attentuation x2 Interpolation Filter Impulse Response, Quad Rate

Overview

The PCM5252 features a configurable miniDSP core. The algorithms for the miniDSP are loaded into the device after power up. The miniDSP has direct access to the digital stereo audio stream, offering the possibility for advanced DSP algorithms with very low group delay. The miniDSP can run up to 1024 instructions on every audio sample at a 48 kHz sample rate.

The PCM5252 Smart Amplifier uses a mix of code sources. ROM based process flow and RAM based process flow. In the program, different algorithms are called from ROM – such as EQ, DRC and Zero Crossing volume control enabling a faster program load.

Smart SOA

The "Safe Operating Area" (SOA) for a loudspeaker is based on its electro-mechanical-thermal model. Depending on a speaker's inefficiency, some of the power is dissipated as heat rather than mechanical/acoustic energy. By understanding the characteristics of the speaker, Smart Amp is able to drive the speaker harder, without causing the speaker to thermally overload; or, suffer voice coil over-exclusion and fail. SMART SOA are parameters that are differentiated by a PPC GUI into coefficients that the algorithm uses.

Smart BASS

Smart Bass is an intelligent True Bass Alignment algorithm. Smart Bass uses the combination of the speaker model and a desired target response selected by the user to equalize the speaker in the bass region. This target response is critical for the sound character and the user can apply the same target response to very different speakers and get the same sound.

In conventional adaptive Bass Boost Algorithms, designers need to vary the amount of bass boost whenever the output volume is changed. This approach is very much an "open loop" process. Smart Bass is a new proprietary algorithm that combines: True bass extension (in bandwidth and amplitude) and Psycho-acoustic bass extension, with a smart adaptive control.

Smart Bass varies the mix of True Bass extension and Psycho-acoustic bass extension in real time, depending on the loudspeakers position in its SOA.

Smart Bass dynamically switches between True Bass and Psycho-acoustic extension based on a number of parameters such as:

  • Capabilities and properties of the speaker, including Q compensation
  • Music type
  • Volume setting
  • Temperature
  • User preferences
  • Designer preferences

Smart Protection

The two main failure mechanisms for loudspeakers are over temperature and over excursion. By modeling the current state of the speaker, Smart Protection adaptively changes various settings in Smart Amplifier to avoid over temperature and over excursion. Design engineers must first provide details of the loudspeaker (driver and enclosure) into the GUI. From there the appropriate coefficients are generated for the algorithm.

Implementing a Real World Design

Traditionally, system developers and hardware engineers use graphic equalizers in trial-and-error fashion to boost the bass for each new speaker until the sound is right (or "good enough" in many cases). However, this typically results in a strange combined response with too much phase shift. This process must be repeated every time a new speaker is selected. The Smart Bass concept uses the GUI to select a desired target response takes the speaker out of the equation. By this approach users can obtain a target response with minimum phase warp and time domain ringing which gives a speedy and tight bass. Conversely, users can select a target response that has lots of ringing to give a classical heavy ‘oomph’ bass.

Digital Output

The PCM5252 supports an SDOUT output. This can be selected within the process flow, and driven out of a GPIO pin selected in the register map (e.g. Page 0 / Register 80). The I2S output can be fed back to the signal host and used for echo cancellation.

Software

Software selection for the PCM5252 is supported through TI's comprehensive PurePathTM Console Development Environment; a powerful, easy-to-use tool designed specifically to simplify development on the PCM5252 platform. Visit the PCM5252 product folder on www.ti.com to learn more about PurePath™ Console and the latest status on available, ready-to-use DSP algorithms.

Process Flow

An example of the default Process Flow available for the PCM5252 in the PurePath™ Console target is shown below:

PCM5252 processflow.gif Figure 58. Example Processflow

This process flow has from input to output:

  • Volume block, from -110 db to +6 dB with 0.5 dB steps, including a fixed gain block of 0dB to 12 dB gain
  • monobass mixer – mixes the bass into mono below the set frequency, useful for systems where left and right speaker shares the same cabinet volume, bypassed when not needed
  • 10 Biquads for filtering and EQ. The PPC GUI have an advanced biquad control where various filter and eq options can be set and controlled.
  • SmartAmp block, containing all the blocks for bass Q compensation, bass alignment, excursion control and power limited
  • Digital monitor output enabled on GPIO3

DAC and Differential Analog Outputs

Analog Outputs

The PCM5252 devices include a two-channel DAC, with differential outputs. Each pin has a full-scale output voltage is 2.1 Vrms with ground center output. This equates to a 4.2 Vrms differential output. A DC-coupled load is supported in addition to an AC-coupled load, if the load resistance conforms to the specification. The PCM5252 DAC outputs on the OUTLP, OUTLN, OUTRP, and OUTRN terminals have market-leading low out-of-band noise, which offer up to 20-dB lower out-of-band noise compared with existing DAC technology.

Many applications require an external low-pass RC filter (470 Ω + 1.2 nF) to provide sufficient out-of-band noise rejection. This RC filter provides the added advantage of improved protection against ESD damage.

The PCM5252 can also support single ended outputs, using OUTLP and OUTRP respectively. A single 470-Ω and 2.2-nF capacitor can be used on each pin in single ended mode.

The choice between VREF and VCOM modes affects the maximum output level. This is explained in Recommended Operating Conditions.

PCM5252 pcm52xx_diff_out_rc_filter.gif Figure 59. Optional Low Pass Filters

Choosing Between VREF and VCOM Modes

VREF mode is the default configuration. This mode allows full 2.1-Vrms signal output. As shown in Recommended Operating Conditions, the minimum AVDD to avoid clipping is 3.2 V.

VCOM mode allows setting a custom common-mode voltage when required by the application. This somewhat limits the output signal swing before clipping.

Voltage Reference and Output Levels

The PCM5252 devices have an internal, fixed band-gap reference voltage, with default operation in VREF mode. No external decoupling capacitor is required for this mode.

The PCM5252 devices can be operated with a common-mode voltage output (VCOM mode) at the VCOM pin by setting Page 1, Register 1, D(0) to 1. In this mode, an external decoupling capacitor is required.

When using this DAC in VREF mode, the output-signal voltage is independent of the power-supply voltage: The D/A conversion gain in VREF mode yields a 2.1-Vrms output voltage with a digital full-scale input. However, in VREF mode, an output waveform may clip due to the limitations that may be present in the analog power supply voltage. On the other hand, the full-scale output voltage in VCOM mode is proportional to the analog power supply AVDD (for example, (2.1 × AVDD / 3.3) Vrms).

Mode Switching Sequence, from VREF Mode to VCOM Mode

Following register setting sequence is recommended for changing VREF mode to VCOM mode.

1. Page 0 / Register 2 RQST = 1: Standby mode
2. Page 1 / Register 8 RCMF = 1: Fast ramp up → on
3. Page 1 / Register 9  VCPD = 0: VCOM is power on
4. Wait 3 ms with external capacitor = 1 µF
5. Page 1 / Register 8 RCMF = 0: Fast ramp up → off
6. Page 1 / Register 1 OSEL = 1: VCOM mode
7. Page 0 / Register 2 RQST = 0: Normal mode

Digital Volume Control

A basic digital volume control with range from 24 dB to –103 dB and mute is available on each channels by Page 0, Resister 61, D(7:0) for L-ch and Register 62, D(7:0) for R-ch. These volume controls all have 0.5-dB step programmability over most gain and attenuation ranges. Table 21 lists the detailed gain versus programmed setting for this basic volume control. Volume can be changed for both L-ch and R-ch at the same time or independently by Page 0, Register 60, D(1:0). When D(1:0) set 00 (default), independent control is selected. When D(1:0) set 01, R-ch accords with L-ch volume. When D(1:0) set 10, L-ch accords with R-ch volume. To set D(1:0) to 11 is prohibited.

NOTE

This volume control is done externally to the miniDSP and only influences the analog DAC output. Any changes to the SDOUT data should be done in the miniDSP process flow.

Table 21. Digital Volume Control Settings

GAIN SETTING BINARY DATA GAIN (dB) COMMENTS
0 0000-0000 24.0 Positive maximum
1 0000-0001 23.5
: :
46 0010-1110 1.0
47 0010-1111 0.5
48 0011-0000 0.0 No attenuation (default)
49 0011-0001 –0.5
50 0011-0010 –1.0
51 0011-0011 –1.5
: :
253 1111-1101 –102.5
254 1111-1110 –103 Negative maximum
255 1111-1111 –∞ Negative infinite (Mute)

Ramp-up frequency and ramp-down frequency can be controlled by Page 0, Register 63, D(7:6) and D(3:2) as shown in Table 22. Also Ramp-up step and ramp-down step can be controlled by Page 0, Register 63 D(5:4) and D(1:0) as shown in Table 23.

Table 22. Ramp-Up or Down Frequency

RAMP-UP SPEED EVERY N fS COMMENTS RAMP-DOWN FREQUENCY EVERY N fS COMMENTS
00 1 Default 00 1 Default
01 2 01 2
10 4 10 4
11 Direct change 11 Direct change

Table 23. Ramp-Up or Down Step

RAMP-UP STEP STEP dB COMMENTS RAMP-DOWN STEP STEP dB COMMENTS
00 4.0 00 -4.0
01 2.0 01 -2.0
10 1.0 Default 10 -1.0 Default
11 0.5 11 -0.5

Emergency Ramp-Down

Digital volume emergency ramp-down by is provided for situations such as I2S clock error and power supply failure. Ramp-down speed is controlled by Page 0, Register 64, D(7:6). Ramp-down step can be controlled by Page 0 Register 64, D(5:4). Default is ramp-down by every fS cycle with –4-dB step.

Analog Gain Control

Analog gain control can be selected between 2-Vrms FS (0 dB) or 1-Vrms FS (–6 dB). Gain is controlled through hardware by the AGNS pin, and through software (SPI/I2C), Page 1, Register 2, D4(L-ch) / D0(R-ch).

Reset and System Clock Functions

Clocking Overview

The PCM5252 devices have flexible systems for clocking. Internally, the device requires a number of clocks, mostly at related clock rates to function correctly. All of these clocks can be derived from the serial audio interface in one form or another.

PCM5252 f_pcm51xx_clk_bd.gif Figure 60. Audio Flow with Respective Clocks

As shown in Figure 60 the data flows at the sample rate (fS). Once the data is brought into the serial audio interface, it gets processed, interpolated and modulated all the way to 128 × fS before arriving at the current segments for the final digital to analog conversion.

The clock tree is shown in Figure 61.

PCM5252 f_pcm51xx_clk_tree_PLL.gif Figure 61. PCM5252 Clock Distribution Tree

The serial audio interface typically has 4 connections: SCK (system master clock), BCK (bit clock), LRCK (left right word clock), and DIN (data). The device has an internal PLL that is used to take either SCK or BCK and create the higher rate clocks required by the interpolating processor and the DAC clock. This allows the device to operate with or without an external SCK.

In situations where the highest audio performance is required, it is suggested that the SCK is brought to the device, along with BCK and LRCK. The device should be configured so that the PLL is only providing a clock source to the miniDSP. By ensuring that the DACCK (DAC Clock) is being driven by the external SCK source, jitter evident in the PLL (in all PLLs) is kept out of the DAC, charge pump, and oversampling system.

Everything else should be a division of the incoming SCK. This is done by setting DAC CLK Source Mux (SDAC in Figure 61) to use SCK as a source, rather than the output of the SCK/PLL Mux. Code examples for this are available in SLASE12.

When the Auto Clock Configuration bit is set (Page 0/ Register 0x25), no additional clocks configuration is required. However, when setting custom PLL values and so forth, the target output rates should match those shown in the recommended PLL values of Table 122.

Clock Slave Mode With Master and System Clock (SCK) Input (4 Wire I2S)

The PCM5252 requires a system clock to operate the digital interpolation filters and advanced segment DAC modulators. The system clock is applied at the SCK input and supports up to 50 MHz. The PCM5252 system-clock detection circuit automatically senses the system-clock frequency. Common audio sampling frequencies in the bands of 8 kHz, 16 kHz, (32 kHz - 44.1 kHz - 48 kHz), (88.2kHz - 96kHz), (176.4 kHz - 192 kHz), and 384 kHz with ±4% tolerance are supported. Values in the parentheses are grouped when detected, (for example, 88.2 kHZ and 96 kHz are detected as double rate, and 32 kHz, 44.1 kHz and 48 kHz are detected as single rate.)

In the presence of a valid bit SCK, BCK and LRCK in software mode, the device will auto-configure the clock tree and PLL to drive the miniDSP as required.

The sampling frequency detector sets the clock for the digital filter, Delta Sigma Modulator (DSM) and the Negative Charge Pump (NCP) automatically. Table 24 shows examples of system clock frequencies for common audio sampling rates.

SCK rates that are not common to standard audio clocks, between 1 MHz and 50 MHz, are only supported in software mode by configuring various PLL and clock-divider registers. This programmability allows the device to become a clock master and drive the host serial port with LRCK and BCK, from a non-audio related clock (for example, using 12 MHz to generate 44.1 kHz [LRCK] and 2.8224 MHz [BCK]).

Table 24. System Master Clock Inputs for Audio Related Clocks

SAMPLING FREQUENCY SYSTEM CLOCK FREQUENCY (fSCK) (MHz)
64 fS 128 fS 192 fS 256 fS 384 fS 512 fS 768 fS 1024 fS 1152 fS 1536 fS 2048 fS 3072 fS
8 kHz (1) 1.024(2) 1.536(2) 2.048 3.072 4.096 6.144 8.192 9.216 12.288 16.384 24.576
16 kHz (1) 2.048(2) 3.072(2) 4.096 6.144 8.192 12.288 16.384 18.432 24.576 36.864 49.152
32 kHz (1) 4.096(2) 6.144(2) 8.192 12.288 16.384 24.576 32.768 36.864 49.152 (1) (1)
44.1 kHz (1) 5.6488(2) 8.4672(2) 11.2896 16.9344 22.5792 33.8688 45.1584 (1) (1) (1) (1)
48 kHz (1) 6.144(2) 9.216(2) 12.288 18.432 24.576 36.864 49.152 (1) (1) (1) (1)
88.2 kHz (1) 11.2896(2) 16.9344 22.5792 33.8688 45.1584 (1) (1) (1) (1) (1) (1)
96 kHz (1) 12.288(2) 18.432 24.576 36.864 49.152 (1) (1) (1) (1) (1) (1)
176.4 kHz (1) 22.579 33.8688 45.1584 (1) (1) (1) (1) (1) (1) (1) (1)
192 kHz (1) 24.576 36.864 49.152 (1) (1) (1) (1) (1) (1) (1) (1)
384 kHz 24.576 49.152 (1) (1) (1) (1) (1) (1) (1) (1) (1) (1)
This system clock rate is not supported for the given sampling frequency.
This system clock rate is supported by PLL mode.

See Timing Requirements: PCM Audio Data for clock timing requirements.

Clock Slave Mode With BCK PLL to Generate Internal Clocks (3-Wire PCM)

The system clock PLL mode allows designers to use a simple 3-wire I2S audio source. The 3-wire source reduces the need for a high frequency SCK, making PCB layout easier, and reduces high frequency electromagnetic interference.

In hardwired mode, the internal PLL is disabled as soon as an external SCK is supplied.

In hardwired mode, the device starts up expecting an external SCK input, but if BCK and LRCK start correctly while SCK remains at ground level for 16 successive LRCK periods, then the internal PLL starts, automatically generating an internal SCK from the BCK reference. Specific BCK rates are required to generate an appropriate master clock. Table 25 describes the minimum and maximum BCK per LRCK for the integrated PLL to automatically generate an internal SCK.

In software mode, the user must set all the PLL registers and clock divider registers for referencing BCK. See Clock Generation Using the PLL for more information. Recommended values can be found in Table 122.

Table 25. BCK Rates (MHz) by LRCK Sample Rate for PCM5252 PLL Operation

  SAMPLE F (kHz)  BCK (fS)
32 64
8
16 1.024
32 1.024 2.048
44.1 1.4112 2.8224
48 1.536 3.072
96 3.072 6.144
192 6.144 12.288
384 12.288 24.576

Clock Generation Using the PLL

The PCM5252 supports a wide range of options to generate the required clocks for the DAC section as well as interface and other control blocks as shown in Figure 61.

The clocks for the PLL require a source reference clock. This clock is sourced as the incoming BCK or SCK. In software mode, a GPIO can also be used.

The source reference clock for the PLL reference clock is selected by programming the SRCREF value on Page 0, Register 13, D(6:4). The PCM5252 provides several programmable clock dividers to achieve a variety of sampling rates for the DAC and clocks for the NCP, OSR and the miniDSP. OSRCK for OSR must be set at 16 fS frequency by DOSR on Page0, Register 30, D(6:0). See Figure 61.

If PLL functionality is not required, set the PLLEN value on Page 0, Register 4, D(0) to 0. In this situation, an external SCK is required.

Table 26. PLL Configuration Registers

CLOCK MULTIPLEXER FUNCTION BITS
SRCREF PLL reference Page 0, Register 13, D(6:4)
DIVIDER FUNCTION BITS
DDSP miniDSP clock divider Page 0, Register 27, D(6:0)
DACCK DAC clock divider Page 0, Register 28, D(6:0)
CPCK NCP clock divider Page 0, Register 29, D(6:0)
OSRCK OSR clock divider Page 0, Register 30, D(6:0)
DBCK External BCK Div Page 0, Register 32, D(6:0)
DLRK External LRCK Div Page 0, Register 33, D(7:0)

PLL Calculation

The PCM5252 has an on-chip PLL with fractional multiplication to generate the clock frequency needed by the audio DAC, Negative Charge Pump, Modulator and Digital Signal Processing blocks. The programmability of the PLL allows operation from a wide variety of clocks that may be available in the system. The PLL input (PLLCKIN) supports clock frequencies from 1 MHz to 50 MHz and is register programmable to enable generation of required sampling rates with fine precision.

The PLL is enabled by default. The PLL can be turned on by writing to Page 0, Register 4, D(0). When the PLL is enabled, the PLL output clock PLLCK is given by Equation 1.

Equation 1. PCM5252 f_pcm51xx_eq_pll_rate_clac.gif

where

  • R = 1, 2, 3,4, ... , 15, 16
  • J = 4,5,6, . . . 63, and D = 0000, 0001, 0002, . . . 9999
  • K = [J value].[D value]
  • P = 1, 2, 3, ... 15

R, J, D, and P are programmable. J is the integer portion of K (the numbers to the left of the decimal point), while D is the fractional portion of K (the numbers to the right of the decimal point, assuming four digits of precision).

Examples:

  • If K = 8.5, then J = 8, D = 5000
  • If K = 7.12, then J = 7, D = 1200
  • If K = 14.03, then J = 14, D = 0300
  • If K = 6.0004, then J = 6, D = 0004

When the PLL is enabled and D = 0000, the following conditions must be satisfied:

  • 1 MHz ≤ ( PLLCKIN / P ) ≤ 20 MHz
  • 64 MHz ≤ (PLLCKIN x K x R / P ) ≤ 100 MHz (in VREF mode)
  • 72 MHz ≤ (PLLCKIN x K x R / P ) ≤ 86 MHz (in VCOM mode)
  • 1 ≤ J ≤ 63

When the PLL is enabled and D ≠ 0000, the following conditions must be satisfied:

  • 6.667 MHz ≤ PLLCLKIN / P ≤ 20 MHz
  • 64 MHz ≤ (PLLCKIN x K x R / P ) ≤ 100 MHz (in VREF mode)
  • 72 MHz ≤ (PLLCK IN x K x R / P ) ≤ 86 MHz (in VCOM mode)
  • 4 ≤ J ≤ 11
  • R = 1

When the PLL is enabled,

  • fS = (PLLCLKIN × K × R) / (2048 × P)
  • The value of N is selected so that fS × N = PLLCLKIN x K x R / P is in the allowable range.

Example: MCLK = 12 MHz and fS = 44.1 kHz, (N=2048)

Select P = 1, R = 1, K = 7.5264, which results in J = 7, D = 5264

Example: MCLK = 12 MHz and fS = 48.0 kHz, (N=2048)

Select P = 1, R = 1, K = 8.192, which results in J = 8, D = 1920

Values are written to the registers in Table 27.

Recommended PLL Settings

Recommended values for the PLL can be found after the register descriptions in this data sheet. Different values are defined based on the device configuration for VREF or VCOM mode.

Other configurations are possible, at your own risk.

Table 27 show the details of the register locations, as well as the nomenclature for the table of registers found at the end of this document.

Table 27. PLL Registers

DIVIDER FUNCTION BITS
PLLE PLL enable Page 0, Register 4, D(0)
PPDV PLL P Page 0, Register 20, D(3:0)
PJDV PLL J Page 0, Register 21, D(5:0)
PDDV PLL D Page 0, Register 22, D(5:0)
Page 0, Register 23, D(7:0)
PRDV PLL R Page 0, Register 24, D(3:0)

Table 28. PLL Configuration Recommendations

COLUMN DESCRIPTION
fS (kHz) Sampling frequency
RSCK Ratio between sampling frequency and SCK frequency (SCK frequency = RSCK × sampling frequency)
SCK (MHz) System master clock frequency at SCK input (pin 20)
PLL VCO (MHz) PLL VCO frequency as PLLCK in Figure 61
P One of the PLL coefficients in Equation 1
PLL REF (MHz) Internal reference clock frequency which is produced by SCK / P
M = K * R The final PLL multiplication factor computed from K and R as described in Equation 1
K = J.D One of the PLL coefficients in Equation 1
R One of the PLL coefficients in Equation 1
PLL fS Ratio between fS and PLL VCO frequency (PLL VCO / fS)
DSP fS Ratio between miniDSP operating clock rate and fS (PLL fS / NMAC)
NMAC The miniDSP clock divider value in Table 26
DSP CLK (MHz) The miniDSP operating frequency as DSPCK in Figure 61
MOD fS Ratio between DAC operating clock frequency and fS (PLL fS / NDAC)
MOD f (kHz) DAC operating frequency as DACCK in Figure 61
NDAC DAC clock divider value in Table 26
DOSR OSR clock divider value in Table 26 for generating OSRCK in Figure 61. DOSR must be chosen so that MOD fS / DOSR = 16 for correct operation.
NCP NCP (negative charge pump) clock divider value in Table 26
CP f Negative charge pump clock frequency (fS × MOD fS / NCP)
% Error Percentage of error between PLL VCO / PLL fS and fS (mismatch error).
  • This number is typically zero but can be non-zero especially when K is not an integer (D is not zero).
  • This number may be non-zero only when the PCM5252 acts as a master.

Clock Master Mode from Audio Rate Master Clock

In Master Mode, the device generates bit clock (BCK) and left-right clock (LRCK) and outputs them on the appropriate pins. To configure the device in this mode, first put the device into reset, then use registers BCKO and LRKO (Pg 0, Reg 9 0x09). Then reset the LRCK and BCK divider counters using bits RBCK and RLRK (Pg 0, Reg 12 0x0C). Finally, exit reset.

An example of this is given in register programming examples in the PCM5242 data sheet (SLASE12.)

Figure 62 shows a simplified serial port clock tree for the device in master mode.

PCM5252 f_pcm51xx_serialport_clk_tree.gif Figure 62. Simplified Clock Tree for SCK Sourced Master Mode

In master mode, SCK is an input and BCK/LRCK are outputs. BCK and LRCK are integer divisions of SCK. Master mode with a non-audio rate master clock source will require external GPIOs to use the PLL in standalone mode.

The PLL will also need to be configured to ensure that the onchip miniDSP processor can be driven at its maximum clock rate.

Register changes that need to be done include switching the device into master mode, and setting the divider ratio.

Here is an example of using 24.576 MCLK as a master clock source and driving the BCK and LRCK with integer dividers to create 48 kHz.

In this mode, the DAC section of the device is also running from the PLL output. While the PLL inside the PCM5252 is one that has been specified to achieve the stated performance, using the SCK CMOS Oscillator source will have less jitter.

To switch the DAC clocks (SDAC in the Figure 61) the following registers should be modified.

  • Clock Tree Flex Mode (Page 253, Registers 0x3F and 0x40)
  • DAC and OSR Source Clock Register (Page 0, Reg 14) – set to 0x30 (SCK input, and OSR is set to whatever the DAC source is)
  • The DAC clock divider should be 16 FS.
    • 16 × 48 kHz = 768 kHz
    • 24.576 MHz (SCK in) / 768 kHz = 32
    • Therefor, divide ratio for register DDAC (Page 0, Reg 28 0x1C) should be set to 32. The may the register is mapped gives 0x00 = 1, so 32 must be converted to 0x1F.

An example configuration can be found in the PCM5242 data sheet (SLASE12).

Clock Master from a Non-Audio Rate Master Clock

The classic example here is running a 12-MHz Master clock for a 48-kHz sampling system. Given the clock tree for the device (shown in Figure 61), a non-audio clock rate cannot be brought into the SCK to the PLL in master mode. Therefore, the PLL source must be configured to be a GPIO pin, and the output brought back into another GPIO pin.

PCM5252 f_pcm51xx_non-aud_mstr_clk.gif Figure 63. Application Diagram for Using Non-Audio Clock Sources to Generate Audio Clocks

The clock flow through the system is shown in Figure 63. The newly-generated SCK must be brought out of the device on a GPIO pin, then brought into the SCK pin for integer division to create BCK and LRCK outputs.

NOTE

Pullup resistors must be used on BCK and LRCK in this mode to ensure the device does not go into sleep mode.

A code example for configuring this mode is provided in the PCM5242 data sheet (SLASE12).

Device Functional Modes

Choosing a Control Mode

SPI Mode is selected by connecting MODE1 to DVDD. SPI Mode uses four signal lines and allows higher-speed full-duplex communication between the host and the PCM5252 device.

I2C Mode is selected by connecting MODE1 to DGND and Mode2 to DVDD. I2C uses two signal lines for half-duplex communication, and is widely used in a variety of devices.

Hardware Control Mode is selected by connecting both MODE1 and MODE2 pins to DGND. Hardware control is useful in applications that do not require on-the-fly device-reconfiguration changes in operating features such as gain or filter latency selection.

See Pin Assignments for a comparison of pin assignments for the 32-pin VQFN.

Software Control

SPI Interface

The SPI interface is a 4-wire synchronous serial port which operates asynchronously to the serial audio interface and the system clock (SCK). The serial control interface is used to program and read the on-chip mode registers.

The control interface includes MISO (pin 24), MOSI (pin 11), MC (pin 12), and MS (pin 18). MISO (Master In Slave Out) is the serial data output, used to read back the values of the mode registers; MOSI (Master Out Slave In) is the serial data input, used to program the mode registers.

MC is the serial bit clock, used to shift data in and out of the control port by falling edge of MC, and MS is the mode control enable with LOW active, used to enable the internal mode register access. If feedback from the device is not required, the MISO pin can be assigned to GPIO1 by register control.

Register Read and Write Operation

All read/write operations for the serial control port use 16-bit data words. Figure 64 shows the control data word format. The most significant bit is the read/write bit. For write operations, the bit must be set to 0. For read operations, the bit must be set to 1. There are seven bits, labeled IDX[6:0], that hold the register index (or address) for the read and write operations. The least significant eight bits, D[7:0], contain the data to be written to, or the data that was read from, the register specified by IDX[6:0].

Figure 64 and Figure 65 show the functional timing diagram to write or read through the serial control port. MS is held at a logic-1 state until a register access. To start the register write or read cycle, set MS to logic 0. Sixteen clocks are then provided on MC, corresponding to the 16 bits of the control data word on MOSI and read-back data on MISO. After the eighth clock cycle has completed, the data from the indexed-mode control register appears on MISO during the read operation. After the sixteenth clock cycle has completed, the data is latched into the indexed-mode control register during the write operation. To write or read subsequent data, MS is set to logic 1 once (see tMHH in Figure 69).

PCM5252 f_pcm51xx_mdi_ctrl_data_word_format.gif Figure 64. Control Data Word Format; MDI

NOTE

B8 is used for selection of Write or Read. Setting = 0 indicates a Write, while = 1 indicates a Read. Bits 15–9 are used for register address. Bits 7–0 are used for register data. Multiple-byte write or read (up to 8 bytes) is supported while MS is kept low. The address field becomes the initial address, automatically incrementing for each byte.

PCM5252 f_pcm51xx_td_ser_ctrl_format_wr.gif Figure 65. Serial Control Format; Write, Single Byte
PCM5252 f_pcm51xx_td_ser_ctrl_format__burst_wr.gif Figure 66. Serial Control Format; Write, Multiple Byte
PCM5252 f_pcm51xx_td_ser_ctrl_format_rd.gif Figure 67. Serial Control Format; Read
PCM5252 f_pcm51xx_td_ser_ctrl_format__burst_rd.gif Figure 68. Serial Control Format; Read, Multiple Byte
PCM5252 f_pcm51xx_td_ctrl_if.gif Figure 69. Control Interface Timing

Table 29. Control Interface Timing

MIN MAX UNIT
tMCY MC Pulse Cycle Time 100 ns
tMCL MC Low Level Time 40 ns
tMCH MC High Level Time 40 ns
tMHH MS High Level Time 20 ns
tMSS MS ↓ Edge to MC ↑ Edge 30 ns
tMSH MS Hold Time(1) 30 ns
tMDH MDI Hold Time 15 ns
tMDS MDI Set-up Time 15 ns
tMOS MC Rise Edge to MDO Stable 20 ns
MC falling edge for LSB to MS rising edge.

I2C Interface

The PCM5252 supports the I2C serial bus and the data transmission protocol for standard and fast mode as a slave device.

In I2C mode, the control terminals are changed as follows.

Table 30. I2C Pins and Functions

SIGNAL PIN I/O DESCRIPTION
SDA 11 I/O I2C data
SCL 12 I I2C clock
ADR2 16 I I2C address 2
ADR1 24 I I2C address 1

Slave Address

Table 31. I2C Slave Address

MSB LSB
1 0 0 1 1 ADR2 ADR1 R/ W

The PCM5252 has 7 bits for its own slave address. The first five bits (MSBs) of the slave address are factory preset to 10011 (0x9x). The next two bits of the address byte are the device select bits which can be user-defined by the ADR1 and ADR0 terminals. A maximum of four devices can be connected on the same bus at one time. This gives a range of 0x98, 0x9A, 0x9C and 0x9E. Each PCM5252 responds when it receives its own slave address.

Register Address Auto-Increment Mode

PCM5252 f_pcm51xx_auto_inc_mode.gif Figure 70. Auto Increment Mode

Auto-increment mode allows multiple sequential register locations to be written to or read back in a single operation, and is especially useful for block write and read operations.

Packet Protocol

A master device must control packet protocol, which consists of start condition, slave address, read/write bit, data if write or acknowledge if read, and stop condition. The PCM5252 supports only slave receivers and slave transmitters.

PCM5252 f_pcm51xx_packet_protocol.gif Figure 71. Packet Protocol

Table 32. Write Operation - Basic I2C Framework

Transmitter M M M S M S M S S M
Data Type St slave address R/ ACK DATA ACK DATA ACK ACK Sp

Table 33. Read Operation - Basic I2C Framework

Transmitter M M M S S M S M M M
Data Type St slave address R/ ACK DATA ACK DATA ACK NACK Sp

M = Master Device; S = Slave Device; St = Start Condition; Sp = Stop Condition

Write Register

A master can write to any PCM5252 registers using single or multiple accesses. The master sends a PCM5252 slave address with a write bit, a register address with auto-increment bit, and the data. If auto-increment is enabled, the address is that of the starting register, followed by the data to be transferred. When the data is received properly, the index register is incremented by 1 automatically. When the index register reaches 0x7F, the next value is 0x0. Table 34 shows the write operation.

Table 34. Write Operation

Transmitter M M M S M S M S M S S M
Data Type St slave addr W ACK inc reg addr ACK write data 1 ACK write data 2 ACK ACK Sp

M = Master Device; S = Slave Device; St = Start Condition; Sp = Stop Condition; W = Write; ACK = Acknowledge

Read Register

A master can read the PCM5252 register. The value of the register address is stored in an indirect index register in advance. The master sends a PCM5252 slave address with a read bit after storing the register address. Then the PCM5252 transfers the data which the index register points to. When auto-increment is enabled, the index register is incremented by 1 automatically. When the index register reaches 0x7F, the next value is 0x0. Table 35 shows the read operation.

Table 35. Read Operation

Transmitter M M M S M S M M M S S M M M
Data Type St slave addr W ACK inc reg addr ACK Sr slave addr R ACK data ACK NACK Sp

M = Master Device; S = Slave Device; St = Start Condition; Sr = Repeated Start Condition; Sp = Stop Condition; W = Write; R = Read; NACK = Not acknowledge

Timing Characteristics

PCM5252 f_pcm51xx_td_reg_rd.gif Figure 72. Register Access Timing

Table 36. I2C Bus Timing

MIN MAX UNIT
fSCL SCL clock frequency Standard 100 kHz
Fast 400 kHz
tBUF Bus free time between a STOP and START condition Standard 4.7 µs
Fast 1.3
tLOW Low period of the SCL clock Standard 4.7 µs
Fast 1.3
tHI High period of the SCL clock Standard 4.0 µs
Fast 600 ns
tRS-SU Setup time for (repeated)START condition Standard 4.7 µs
Fast 600 ns
tS-HD Hold time for (repeated)START condition Standard 4.0 µs
tRS-HD Fast 600 ns
tD-SU Data setup time Standard 250 ns
Fast 100
tD-HD Data hold time Standard 0 900 ns
Fast 0 900
tSCL-R Rise time of SCL signal Standard 20 + 0.1CB 1000 ns
Fast 20 + 0.1CB 300
tSCL-R1 Rise time of SCL signal after a repeated START condition and after an acknowledge bit Standard 20 + 0.1CB 1000 ns
Fast 20 + 0.1CB 300
tSCL-F Fall time of SCL signal Standard 20 + 0.1CB 1000 ns
Fast 20 + 0.1CB 300
tSDA-R Rise time of SDA signal Standard 20 + 0.1CB 1000 ns
Fast 20 + 0.1CB 300
tSDA-F Fall time of SDA signal Standard 20 + 0.1CB 1000 ns
Fast 20 + 0.1CB 300
tP-SU Setup time for STOP condition Standard 4.0 µs
Fast 600 ns
CB Capacitive load for SDA and SCL line 400 pF
tSP Pulse width of spike suppressed Fast 50 ns
VNH Noise margin at High level for each connected device (including hysteresis) 0.2 × VDD V

VREF and VCOM Modes

See Choosing Between VREF and VCOM Modes for information on configuring these modes.