SLDS204B October 2014 – June 2020 PGA300
PRODUCTION DATA.
The last byte of the EEPROM memory, which is the EEPROM_CRC_VALUE_USER register, is reserved for the memory map CRC. This CRC value covers all data in the EEPROM memory. Every time the EEPROM_CRC_VALUE_USER register is written, the PGA300 calculates the CRC value across the EEPROM memory, places the calculated CRC value in the EEPROM_CRC_VALUE_CALC register, and validates the value against the CRC value programmed in the EEPROM_CRC_VALUE_USER register. If the calculated CRC value in the EEPROM_CRC_VALUE_CALC register matches the value programmed in the EEPROM_CRC_VALUE_USER register, the CRC_GOOD bit is set in the EEPROM_CRC_STATUS register.
The CRC check can also be initiated at any time by setting the CALCULATE_CRC bit in the EEPROM_CRC register. The status of the CRC calculation is available in the CRC_CHECK_IN_PROG bit in the EEPROM_CRC_STATUS register, whereas the result of the CRC validation is available in the CRC_GOOD bit in the EEPROM_CRC_STATUS register.
The CRC calculation pseudo code is as follows:
currentCRC8 = 0xFF; // Current value of CRC8
for NextData
D = NextData;
C = currentCRC8;
begin
nextCRC8_BIT0 = D_BIT7 ^ D_BIT6 ^ D_BIT0 ^ C_BIT0 ^ C_BIT6 ^ C_BIT7;
nextCRC8_BIT1 = D_BIT6 ^ D_BIT1 ^ D_BIT0 ^ C_BIT0 ^ C_BIT1 ^ C_BIT6;
nextCRC8_BIT2 = D_BIT6 ^ D_BIT2 ^ D_BIT1 ^ D_BIT0 ^ C_BIT0 ^ C_BIT1 ^ C_BIT2 ^ C_BIT6;
nextCRC8_BIT3 = D_BIT7 ^ D_BIT3 ^ D_BIT2 ^ D_BIT1 ^ C_BIT1 ^ C_BIT2 ^ C_BIT3 ^ C_BIT7;
nextCRC8_BIT4 = D_BIT4 ^ D_BIT3 ^ D_BIT2 ^ C_BIT2 ^ C_BIT3 ^ C_BIT4;
nextCRC8_BIT5 = D_BIT5 ^ D_BIT4 ^ D_BIT3 ^ C_BIT3 ^ C_BIT4 ^ C_BIT5;
nextCRC8_BIT6 = D_BIT6 ^ D_BIT5 ^ D_BIT4 ^ C_BIT4 ^ C_BIT5 ^ C_BIT6;
nextCRC8_BIT7 = D_BIT7 ^ D_BIT6 ^ D_BIT5 ^ C_BIT5 ^ C_BIT6 ^ C_BIT7;
end
currentCRC8 = nextCRC8_D8;
endfor
NOTE
The EEPROM CRC calculation is complete 340 µs after the digital core starts running at power up.