SLDS204B October   2014  – June 2020 PGA300

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      PGA300 Simplified Block Diagram
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics: Reverse Voltage Protection
    6. 6.6  Electrical Characteristics: Regulators
    7. 6.7  Electrical Characteristics: Internal References
    8. 6.8  Electrical Characteristics: Bridge Sensor Supply
    9. 6.9  Electrical Characteristics: External Temperature Sensor Supply
    10. 6.10 Electrical Characteristics: Internal Temperature Sensor
    11. 6.11 Electrical Characteristics: P Gain Stage (Chopper Stabilized)
    12. 6.12 Electrical Characteristics: P Analog-to-Digital Converter
    13. 6.13 Electrical Characteristics: T Gain Stage (Chopper Stabilized)
    14. 6.14 Electrical Characteristics: T Analog-to-Digital Converter
    15. 6.15 Electrical Characteristics: DAC Output
    16. 6.16 Electrical Characteristics: DAC Gain Stage
    17. 6.17 Electrical Characteristics: Diagnostics
    18. 6.18 Electrical Characteristics: One-Wire Interface
    19. 6.19 Electrical Characteristics: EEPROM (Non-Volatile Memory)
    20. 6.20 Electrical Characteristics: Power-Supply Currents
    21. 6.21 Electrical Characteristics: Timing
    22. 6.22 Electrical Characteristics: Accuracy
    23. 6.23 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Reverse-Voltage Protection Circuit
      2. 7.3.2  Linear Regulators
      3. 7.3.3  Internal References
        1. 7.3.3.1 High-Voltage Reference
        2. 7.3.3.2 Accurate Reference
      4. 7.3.4  Bridge Sensor Supply for Resistive Bridges (BRG+ to BRG–)
      5. 7.3.5  ITEMP Supply for External Temperature Sensors
      6. 7.3.6  Internal Temperature Sensor
      7. 7.3.7  Pressure Measurement Signal Chain
        1. 7.3.7.1 P Gain Stage
        2. 7.3.7.2 P Analog-to-Digital Converter
          1. 7.3.7.2.1 P Sigma-Delta Modulator for P ADC
          2. 7.3.7.2.2 P Decimation Filter for P ADC
      8. 7.3.8  Temperature Measurement Signal Chain
        1. 7.3.8.1 T Gain Stage
        2. 7.3.8.2 T Analog-to-Digital Converter
          1. 7.3.8.2.1 T Sigma-Delta Modulator for T ADC
          2. 7.3.8.2.2 T Decimation Filters for T ADC
      9. 7.3.9  DAC Output
        1. 7.3.9.1 Ratiometric vs Absolute Output Mode
      10. 7.3.10 DAC Gain Stage
      11. 7.3.11 Digital Compensation and Filter
        1. 7.3.11.1 Digital Gain and Offset Compensation
        2. 7.3.11.2 Temperature and Nonlinearity Compensation
          1. 7.3.11.2.1 Operating Without TC and NL Compensation
          2. 7.3.11.2.2 Temperature Compensation Using the Internal Temperature Sensor
        3. 7.3.11.3 Clamping
        4. 7.3.11.4 Digital IIR Filter
          1. 7.3.11.4.1 Filter Coefficients
            1. 7.3.11.4.1.1 No Filtering
            2. 7.3.11.4.1.2 Filter Coefficients for P ADC Sampling Rate = 128 µs
      12. 7.3.12 Diagnostics
        1. 7.3.12.1 Power-Supply Diagnostics
        2. 7.3.12.2 Signal Chain Diagnostics
          1. 7.3.12.2.1 P Gain and T Gain Input Diagnostics
          2. 7.3.12.2.2 P Gain and T Gain Output Diagnostics
          3. 7.3.12.2.3 Masking Signal Chain Diagnostics
        3. 7.3.12.3 Fault Detection Timing
    4. 7.4 Device Functional Modes
      1. 7.4.1 Operating Modes
        1. 7.4.1.1 Execution Mode
        2. 7.4.1.2 Configuration Mode
      2. 7.4.2 Output Modes
        1. 7.4.2.1 Voltage Output Mode
        2. 7.4.2.2 Current Output Mode
    5. 7.5 Programming
      1. 7.5.1 One-Wire Interface (OWI)
        1. 7.5.1.1 Overview of OWI
        2. 7.5.1.2 Activating and Deactivating the OWI
          1. 7.5.1.2.1 Activating OWI Communication
          2. 7.5.1.2.2 Deactivating OWI Communication
        3. 7.5.1.3 OWI Protocol
          1. 7.5.1.3.1 OWI Frame Structure
            1. 7.5.1.3.1.1 Standard Field Structure
            2. 7.5.1.3.1.2 Frame Structure
            3. 7.5.1.3.1.3 Sync Field
            4. 7.5.1.3.1.4 Command Field
            5. 7.5.1.3.1.5 Data Fields
          2. 7.5.1.3.2 OWI Commands
            1. 7.5.1.3.2.1 OWI Write Command
            2. 7.5.1.3.2.2 OWI Read-Initialization Command
            3. 7.5.1.3.2.3 OWI Read-Response Command
            4. 7.5.1.3.2.4 OWI EEPROM Cache Burst-Write Command
            5. 7.5.1.3.2.5 OWI EEPROM Cache Burst-Read Command
          3. 7.5.1.3.3 OWI Operations
            1. 7.5.1.3.3.1 Write Operation
            2. 7.5.1.3.3.2 Read Operation
            3. 7.5.1.3.3.3 EEPROM Cache Burst Write
            4. 7.5.1.3.3.4 EEPROM Cache Burst Read
      2. 7.5.2 Memory
        1. 7.5.2.1 EEPROM Memory
          1. 7.5.2.1.1 EEPROM Cache
          2. 7.5.2.1.2 EEPROM Programming Procedure
          3. 7.5.2.1.3 EEPROM Programming Current
          4. 7.5.2.1.4 EEPROM Memory Map CRC
      3. 7.5.3 Control and Status Registers
    6. 7.6 Register Maps
      1. 7.6.1 Register Settings
      2. 7.6.2 Control and Status Registers
      3. 7.6.3 EEPROM Registers
      4. 7.6.4 Register Descriptions
        1. 7.6.4.1  MODE_CTRL Register (CS Register Page: 0x0) (CS Offset: 0x0C) (EEPROM Page: N/A) (EEPROM Offset: N/A)
          1. Table 14. MODE_CTRL Field Descriptions
        2. 7.6.4.2  PADC_DATA_LSB and PADC_DATA_MSB Registers (CS Register Page: 0x2) (CS Offset: 0x20, 0x21) (EEPROM Page: N/A) (EEPROM Offset: N/A)
        3. 7.6.4.3  TADC_DATA_LSB and TADC_DATA_MSB Registers (CS Register Page: 0x2) (CS Offset: 0x24, 0x25) (EEPROM Page: N/A) (EEPROM Offset: N/A)
        4. 7.6.4.4  DAC_REG_LSB and DAC_REG_MSB Registers (CS Register Page: 0x2) (CS Offset: 0x30, 0x31) (EEPROM Page: N/A) (EEPROM Offset: N/A)
        5. 7.6.4.5  TC and NL Compensation Coefficient (hx, gx, nx, and mx) Registers (CS Register Page: N/A) (CS Offset: N/A) (EEPROM Page: see ) (EEPROM Offset: see )
        6. 7.6.4.6  Digital Filter Coefficient (ax and bx) Registers (CS Register Page: N/A) (CS Offset: N/A) (EEPROM Page: see ) (EEPROM Offset: see )
        7. 7.6.4.7  NORMAL_LOW_LSB and NORMAL_LOW_MSB Registers (CS Register Page: N/A) (CS Offset: N/A) (EEPROM Page: 0x5) (EEPROM Offset: 0x02, 0x03)
        8. 7.6.4.8  NORMAL_HIGH_LSB and NORMAL_HIGH_MSB Registers (CS Register Page: N/A) (CS Offset: N/A) (EEPROM Page: 0x5) (EEPROM Offset: 0x04, 0x05)
        9. 7.6.4.9  LOW_CLAMP_LSB and LOW_CLAMP_MSB Registers (CS Register Page: N/A) (CS Offset: N/A) (EEPROM Page: 0x5) (EEPROM Offset: 0x06, 0x07)
        10. 7.6.4.10 HIGH_CLAMP_LSB and HIGH_CLAMP_MSB Registers (CS Register Page: N/A) (CS Offset: N/A) (EEPROM Page: 0x6) (EEPROM Offset: 0x00, 0x01)
        11. 7.6.4.11 PADC_GAIN_LSB and PADC_GAIN_MSB Registers (CS Register Page: N/A) (CS Offset: N/A) (EEPROM Page: 0x6) (EEPROM Offset: 0x02, 0x03)
        12. 7.6.4.12 PADC_OFFSET_LSB and PADC_OFFSET_MSB Registers (CS Register Page: N/A) (CS Offset: N/A) (EEPROM Page: 0x6) (EEPROM Offset: 0x04, 0x05)
        13. 7.6.4.13 DAC_FAULT_LSB and DAC_FAULT_MSB Registers (CS Register Page: N/A) (CS Offset: N/A) (EEPROM Page: 0x9) (EEPROM Offset: 0x02, 0x03)
        14. 7.6.4.14 TADC_GAIN_LSB and TADC_GAIN_MSB Registers (CS Register Page: N/A) (CS Offset: N/A) (EEPROM Page: 0x9) (EEPROM Offset: 0x04, 0x05)
        15. 7.6.4.15 TADC_OFFSET_LSB and TADC_OFFSET_MSB Registers (CS Register Page: N/A) (CS Offset: N/A) (EEPROM Page: 0x9) (EEPROM Offset: 0x06, 0x07)
        16. 7.6.4.16 SERIAL_NUMBER_BYTE0/1/2/3 Registers (CS Register Page: N/A) (CS Offset: N/A) (EEPROM Page: 0xA) (EEPROM Offset: 0x00, 0x01, 0x02, 0x03)
        17. 7.6.4.17 DAC_CONFIG Register (CS Register Page: 0x2) (CS Offset: 0x39) (EEPROM Page: 0x4) (EEPROM Offset: 0x00)
          1. Table 15. DAC_CONFIG Register Field Descriptions
        18. 7.6.4.18 OP_STAGE_CTRL Register (CS Register Page: 0x2) (CS Offset: 0x3B) (EEPROM Page: 0x4) (EEPROM Offset: 0x01)
          1. Table 16. OP_STAGE_CTRL Register Field Descriptions
        19. 7.6.4.19 TEST_CTRL Register (CS Register Page: 0x02) (CS Offset: 0x67) (EEPROM Page: N/A) (EEPROM Offset: N/A)
          1. Table 17. TEST_CTRL Register Field Descriptions
        20. 7.6.4.20 BRDG_CTRL Register (CS Register Page: 0x2) (CS Offset: 0x46) (EEPROM Page: 0x4) (EEPROM Offset: 0x02)
          1. Table 18. BRDG_CTRL Register Field Descriptions
        21. 7.6.4.21 P_GAIN_SELECT Register (CS Register Page: 0x2) (CS Offset: 0x47) (EEPROM Page: 0x4) (EEPROM Offset: 0x03)
          1. Table 19. P_GAIN_SELECT Register Field Descriptions
        22. 7.6.4.22 T_GAIN_SELECT Register (CS Register Page: 0x2) (CS Offset: 0x48) (EEPROM Page: 0x4) (EEPROM Offset: 0x04)
          1. Table 20. T_GAIN_SELECT Register Field Descriptions
        23. 7.6.4.23 TEMP_CTRL Register (CS Register Page: 0x2) (CS Offset: 0x4C) (EEPROM Page: 0x4) (EEPROM Offset: 0x05)
          1. Table 21. TEMP_CTRL Register Field Descriptions
        24. 7.6.4.24 TEMP_SE Register (CS Register Page: N/A) (CS Offset: N/A) (EEPROM Page: 0x5) (EEPROM Offset: 0x00)
          1. Table 22. TEMP_SE Register Field Descriptions
        25. 7.6.4.25 DIAG_ENABLE Register (CS Register Page: N/A) (CS Offset: N/A) (EEPROM Page: 0x8) (EEPROM Offset: 0x04)
          1. Table 23. DIAG_ENABLE Register Field Descriptions
        26. 7.6.4.26 AFEDIAG_MASK Register (CS Register Page: N/A) (CS Offset: N/A) (EEPROM Page: 0x8) (EEPROM Offset: 0x07)
          1. Table 24. AFEDIAG_MASK Register Field Descriptions
        27. 7.6.4.27 AFEDIAG_CFG Register (CS Register Page: N/A) (CS Offset: N/A) (EEPROM Page: 0x8) (EEPROM Offset: 0x06)
          1. Table 25. AFEDIAG_CFG Register Field Descriptions
        28. 7.6.4.28 AFEDIAG (CS Register Page: 0x2) (CS Offset: 0x5A) (EEPROM Page: N/A) (EEPROM Offset: N/A)
          1. Table 26. AFEDIAG Register Field Descriptions
        29. 7.6.4.29 EEPROM_LOCK Register (CS Register Page: N/A) (CS Offset: N/A) (EEPROM Page: 0x8) (EEPROM Offset: 0x05)
          1. Table 27. EEPROM_LOCK Field Descriptions
        30. 7.6.4.30 EEPROM_PAGE_ADDRESS Register (CS Register Page: 0x5) (CS Offset: 0x88) (EEPROM Page: N/A) (EEPROM Offset: N/A)
          1. Table 28. EEPROM_PAGE_ADDRESS Field Descriptions
        31. 7.6.4.31 EEPROM_CTRL Register (CS Register Page: 0x5) (CS Offset: 0x89) (EEPROM Page: N/A) (EEPROM Offset: N/A)
          1. Table 29. EEPROM_CTRL Field Descriptions
        32. 7.6.4.32 EEPROM_STATUS Register (CS Register Page: 0x5) (CS Offset: 0x8B) (EEPROM Page: N/A) (EEPROM Offset: N/A)
          1. Table 30. EEPROM_STATUS Field Descriptions
        33. 7.6.4.33 EEPROM_CRC Register (CS Register Page: 0x5) (CS Offset: 0x8A) (EEPROM Page: N/A) (EEPROM Offset: N/A)
          1. Table 31. EEPROM_CRC Field Descriptions
        34. 7.6.4.34 EEPROM_CRC_STATUS Register (CS Register Page: 0x5) (CS Offset: 0x8C) (EEPROM Page: N/A) (EEPROM Offset: N/A)
          1. Table 32. EEPROM_CRC_STATUS Field Descriptions
        35. 7.6.4.35 EEPROM_CRC_VALUE_CALC Register (CS Register Page: 0x5) (CS Offset: 0x8D) (EEPROM Page: N/A) (EEPROM Offset: N/A)
          1. Table 33. EEPROM_CRC_VALUE_CALC Field Descriptions
        36. 7.6.4.36 EEPROM_CRC_VALUE_USER Register (CS Register Page: N/A) (CS Offset: N/A) (EEPROM Page: 0xF) (EEPROM Offset: 0x07)
          1. Table 34. EEPROM_CRC_VALUE_USER Field Descriptions
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Harness Open-Wire Diagnostics
    2. 8.2 Typical Applications
      1. 8.2.1 4-mA to 20-mA Current Output
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 External Components
          2. 8.2.1.2.2 Programming and EEPROM Settings
        3. 8.2.1.3 Application Curve
      2. 8.2.2 0-V to 10-V Absolute Voltage Output
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
          1. 8.2.2.2.1 External Components
            1. 8.2.2.2.1.1 Programming and EEPROM Settings
      3. 8.2.3 0-V to 5-V Ratiometric Voltage Output
        1. 8.2.3.1 Design Requirements
        2. 8.2.3.2 Detailed Design Procedure
          1. 8.2.3.2.1 External Components
          2. 8.2.3.2.2 Programming and EEPROM Settings
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.3.11.4.1.2 Filter Coefficients for P ADC Sampling Rate = 128 µs

Table 5 shows the different filter coefficients that must be programmed to achieve a certain filter cutoff frequency.

Table 5. Filter Cutoff Frequency and Filter Coefficients

CUTOFF FREQUENCY (Hz) a0 a1 a2 b0 b1 b2
600 0x4000 0xAAA1 0x2060 0x0B01 0x1602 0x0B01
700 0x4000 0xB169 0x1CEE 0x0E57 0x1CAF 0x0E57
800 0x4000 0xB818 0x19E0 0x11F8 0x23F0 0x11F8
900 0x4000 0xBEAE 0x172D 0x15DB 0x2BB7 0x15DB
1000 0x4000 0xC52D 0x14CE 0x19FB 0x33F6 0x19FB
1100 0x4000 0xCB95 0x12BC 0x1E52 0x3CA3 0x1E52
1200 0x4000 0xD1EA 0x10F2 0x22DC 0x45B8 0x22DC
1300 0x4000 0xD82D 0x0F6A 0x2798 0x4F2F 0x2798
1400 0x4000 0xDE61 0x0E21 0x2C82 0x5905 0x2C82
1500 0x4000 0xE487 0x0D14 0x319B 0x6336 0x319B
1600 0x4000 0xEAA3 0x0C3F 0x36E2 0x6DC4 0x36E2
1700 0x4000 0xF0B6 0x0BA1 0x3C56 0x78AD 0x3C56
1800 0x4000 0xF6C3 0x0B37 0x41FA 0x83F4 0x41FA
1900 0x4000 0xFCCC 0x0B02 0x47CE 0x8F9C 0x47CE
2000 0x4000 0x02D4 0x0B01 0x4DD4 0x9BA9 0x4DD4
2100 0x4000 0x08DD 0x0B33 0x540F 0xA81F 0x540F
2200 0x4000 0x0EE9 0x0B99 0x5A82 0xB504 0x5A82
2300 0x4000 0x14FC 0x0C33 0x612F 0xC25E 0x612F
2400 0x4000 0x1B17 0x0D05 0x681B 0xD037 0x681B
2500 0x4000 0x213C 0x0E0F 0x6F4B 0xDE96 0x6F4B