JAJSCC2 July   2016 SM320C6457-HIREL

PRODUCTION DATA.  

  1. 1デバイスの概要
    1. 1.1 特長
    2. 1.2 アプリケーション
    3. 1.3 概要
    4. 1.4 概要(続き)
    5. 1.5 機能ブロック図
  2. 2改訂履歴
  3. 3Terminal Configuration and Functions
    1. 3.1 Pin Diagram
    2. 3.2 Pin Attributes
      1. 3.2.1 Pin Map
    3. 3.3 Signal Descriptions
  4. 4Specifications
    1. 4.1 Absolute Maximum Ratings
    2. 4.2 ESD Ratings
    3. 4.3 Recommended Operating Conditions
    4. 4.4 Electrical Characteristics
    5. 4.5 Thermal Resistance Characteristics
    6. 4.6 Timing and Switching Characteristics
      1. 4.6.1 Timing Parameters and Information
        1. 4.6.1.1 1.8-V Signal Transition Levels
        2. 4.6.1.2 3.3-V Signal Transition Levels
        3. 4.6.1.3 3.3-V Signal Transition Rates
        4. 4.6.1.4 Timing Parameters and Board Routing Analysis
      2. 4.6.2 Power Supply Sequencing
        1. 4.6.2.1 Power-Supply Decoupling
        2. 4.6.2.2 Power-Down Operation
        3. 4.6.2.3 Power Supply to Peripheral I/O Mapping
      3. 4.6.3 Reset Timing
      4. 4.6.4 Clock and Control Signal Transition Behavior
    7. 4.7 Peripherals
      1. 4.7.1  Enhanced Direct Memory Access (EDMA3) Controller
        1. 4.7.1.1 EDMA3 Device-Specific Information
        2. 4.7.1.2 EDMA3 Channel Synchronization Events
        3. 4.7.1.3 EDMA3 Peripheral Register Description(s)
      2. 4.7.2  Interrupts
        1. 4.7.2.1 Interrupt Sources and Interrupt Controller
        2. 4.7.2.2 External Interrupts Electrical Data/Timing
      3. 4.7.3  Reset Controller
        1. 4.7.3.1 Power-on Reset (POR Pin)
        2. 4.7.3.2 Warm Reset (RESET Pin)
        3. 4.7.3.3 System Reset
        4. 4.7.3.4 CPU Reset
        5. 4.7.3.5 Reset Priority
        6. 4.7.3.6 Reset Controller Register
          1. 4.7.3.6.1 Reset Type Status Register
          2. 4.7.3.6.2 Software Reset Control Register
          3. 4.7.3.6.3 Reset Configuration Register
      4. 4.7.4  PLL1 and PLL1 Controller
        1. 4.7.4.1 PLL1 Controller Device-Specific Information
          1. 4.7.4.1.1 Internal Clocks and Maximum Operating Frequencies
          2. 4.7.4.1.2 PLL1 Controller Operating Modes
          3. 4.7.4.1.3 PLL1 Stabilization, Lock, and Reset Times
        2. 4.7.4.2 PLL1 Controller Memory Map
        3. 4.7.4.3 PLL1 Controller Registers
          1. 4.7.4.3.1  PLL1 Control Register
          2. 4.7.4.3.2  PLL Multiplier Control Register
          3. 4.7.4.3.3  PLL Post-Divider Control Register
          4. 4.7.4.3.4  PLL Controller Divider 3 Register
          5. 4.7.4.3.5  PLL Controller Divider 6 Register
          6. 4.7.4.3.6  PLL Controller Divider 7 Register
          7. 4.7.4.3.7  PLL Controller Divider 8 Register
          8. 4.7.4.3.8  PLL Controller Command Register
          9. 4.7.4.3.9  PLL Controller Status Register
          10. 4.7.4.3.10 PLL Controller Clock Align Control Register
          11. 4.7.4.3.11 PLLDIV Ratio Change Status Register
          12. 4.7.4.3.12 SYSCLK Status Register
        4. 4.7.4.4 PLL1 Controller Input and Output Electrical Data/Timing
      5. 4.7.5  PLL2
        1. 4.7.5.1 PLL2 Device-Specific Information
          1. 4.7.5.1.1 Internal Clocks and Maximum Operating Frequencies
          2. 4.7.5.1.2 PLL2 Operating Modes
        2. 4.7.5.2 PLL2 Input Clock Electrical Data/Timing
      6. 4.7.6  DDR2 Memory Controller
        1. 4.7.6.1 DDR2 Memory Controller Device-Specific Information
        2. 4.7.6.2 DDR2 Memory Controller Peripheral Register Description(s)
        3. 4.7.6.3 DDR2 Memory Controller Electrical Data/Timing
      7. 4.7.7  External Memory Interface A (EMIFA)
        1. 4.7.7.1 EMIFA Device-Specific Information
        2. 4.7.7.2 EMIFA Peripheral Register Description(s)
        3. 4.7.7.3 EMIFA Electrical Data/Timing
          1. 4.7.7.3.1 AECLKIN and AECLKOUT Timing
          2. 4.7.7.3.2 Asynchronous Memory Timing
          3. 4.7.7.3.3 Programmable Synchronous Interface Timing
      8. 4.7.8  I2C Peripheral
        1. 4.7.8.1 I2C Device-Specific Information
        2. 4.7.8.2 I2C Peripheral Register Description(s)
        3. 4.7.8.3 I2C Electrical Data/Timing
          1. 4.7.8.3.1 Inter-Integrated Circuits (I2C) Timing
      9. 4.7.9  Host-Port Interface (HPI) Peripheral
        1. 4.7.9.1 HPI Device-Specific Information
        2. 4.7.9.2 HPI Peripheral Register Description(s)
        3. 4.7.9.3 HPI Electrical Data/Timing
      10. 4.7.10 Multichannel Buffered Serial Port (McBSP)
        1. 4.7.10.1 McBSP Device-Specific Information
          1. 4.7.10.1.1 McBSP Peripheral Register Description(s)
        2. 4.7.10.2 McBSP Electrical Data/Timing
      11. 4.7.11 Ethernet MAC (EMAC)
        1. 4.7.11.1 EMAC Device-Specific Information
        2. 4.7.11.2 EMAC Peripheral Register Description(s)
        3. 4.7.11.3 EMAC Electrical Data/Timing (SGMII)
      12. 4.7.12 Management Data Input/Output (MDIO)
        1. 4.7.12.1 MDIO Peripheral Register Description(s)
        2. 4.7.12.2 MDIO Electrical Data/Timing
      13. 4.7.13 Timers
        1. 4.7.13.1 Timers Device-Specific Information
          1. 4.7.13.1.1 Timer Watchdog Select
        2. 4.7.13.2 Timers Peripheral Register Description(s)
        3. 4.7.13.3 Timers Electrical Data/Timing
      14. 4.7.14 Enhanced Viterbi-Decoder Coprocessor (VCP2)
        1. 4.7.14.1 VCP2 Device-Specific Information
        2. 4.7.14.2 VCP2 Peripheral Register Description
      15. 4.7.15 Enhanced Turbo Decoder Coprocessor (TCP2)
        1. 4.7.15.1 TCP2 Device-Specific Information
      16. 4.7.16 UTOPIA
        1. 4.7.16.1 UTOPIA Device-Specific Information
        2. 4.7.16.2 UTOPIA Peripheral Register Description(s)
        3. 4.7.16.3 UTOPIA Electrical Data/Timing
      17. 4.7.17 Serial RapidIO (SRIO) Port
        1. 4.7.17.1 Serial RapidIO Device-Specific Information
        2. 4.7.17.2 Serial RapidIO Peripheral Register Description(s)
        3. 4.7.17.3 Serial RapidIO Electrical Data/Timing
      18. 4.7.18 General-Purpose Input/Output (GPIO)
        1. 4.7.18.1 GPIO Device-Specific Information
        2. 4.7.18.2 GPIO Peripheral Register Description(s)
        3. 4.7.18.3 GPIO Electrical Data/Timing
      19. 4.7.19 Emulation Features and Capability
        1. 4.7.19.1 Advanced Event Triggering (AET)
        2. 4.7.19.2 Trace
          1. 4.7.19.2.1 Trace Electrical Data/Timing
        3. 4.7.19.3 IEEE 1149.1 JTAG
          1. 4.7.19.3.1 IEEE 1149.1 JTAG Compatibility Statement
          2. 4.7.19.3.2 JTAG Electrical Data/Timing
          3. 4.7.19.3.3 HS-RTDX Electrical Data/Timing
  5. 5Detailed Description
    1. 5.1 Device Overview
    2. 5.2 CPU (DSP Core) Description
    3. 5.3 C64x+ Megamodule
      1. 5.3.1 Memory Architecture
        1. 5.3.1.1 L1P Memory
        2. 5.3.1.2 L1D Memory
        3. 5.3.1.3 L2 Memory
        4. 5.3.1.4 L3 Memory
      2. 5.3.2 Memory Protection
      3. 5.3.3 Bandwidth Management
      4. 5.3.4 Power-Down Control
      5. 5.3.5 Megamodule Resets
      6. 5.3.6 Megamodule Revision
      7. 5.3.7 C64x+ Megamodule Register Descriptions
    4. 5.4 Memory Map Summary
    5. 5.5 Device Configuration
      1. 5.5.1 Device Configuration at Device Reset
      2. 5.5.2 Peripheral Selection After Device Reset
      3. 5.5.3 Device State Control Registers
      4. 5.5.4 Device Status Register Description
      5. 5.5.5 JTAG ID (JTAGID) Register Description
      6. 5.5.6 Pullup/Pulldown Resistors
    6. 5.6 System Interconnect
      1. 5.6.1 Internal Buses, Bridges, and Switch Fabrics
      2. 5.6.2 Data Switch Fabric Connections
      3. 5.6.3 Configuration Switch Fabric
      4. 5.6.4 Bus Priorities
    7. 5.7 Boot Modes
      1. 5.7.1 Second-Level Bootloaders
      2. 5.7.2 Boot Sequence
    8. 5.8 Rake Search Accelerator (RSA)
  6. 6デバイスおよびドキュメントのサポート
    1. 6.1 デバイスの項目表記
    2. 6.2 ツールとソフトウェア
    3. 6.3 ドキュメントのサポート
      1. 6.3.1 ドキュメントの更新通知を受け取る方法
    4. 6.4 Community Resources
    5. 6.5 商標
    6. 6.6 静電気放電に関する注意事項
    7. 6.7 用語集
  7. 7メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
  • GMH|688
サーマルパッド・メカニカル・データ
発注情報

5 Detailed Description

5.1 Device Overview

Table 5-1 provides an overview of the SM320C6457-HIREL DSP. The table shows significant features of the SM320C6457-HIREL device, including the capacity of on-chip RAM, the peripherals, the CPU frequency, and the package and pin count.

Table 5-1 Characteristics of the SM320C6457-HIREL Processor

HARDWARE FEATURES SM320C6457-HIREL
Peripherals EMIFA (64-bit bus width) (clock source = AECLKIN or SYSCLK7) 1
DDR2 Memory Controller (32-bit bus width) [1.8 V I/O] (clock source = DDRREFCLKN|P) 1
EDMA3 (64 independent channels) [CPU/3 clock rate] 1
High-speed 1×/4× Serial RapidIO Port (4 lanes) 1
I2C 1
HPI (32-or 16-bit user selectable) 1 (HPI16 or HPI32)
McBSPs (internal or external clock source up to 100 Mbps) 2
UTOPIA (8-bit mode, 50-MHz, slave-only) 1
10/100/1000 Ethernet MAC (EMAC) 1
Management Data Input/Output (MDIO) 1
64-Bit Timers (configurable) (internal clock source = CPU/6 clock frequency) 2 64-bit or 4 32-bit
General-Purpose Input/Output Port (GPIO) 16
Decoder Coprocessors VCP2 (clock source = CPU/3 clock frequency) 1
TCP2 (clock source = CPU/3 clock frequency) 2
On-Chip Memory Size (Bytes) 2176K
Organization 32KB L1 Program Memory Controller [SRAM/Cache] 32KB L1 Data Memory Controller [SRAM/Cache] 2048KB L2 Unified Memory/Cache 64KB L3 ROM
C64x+ Megamodule Revision ID Megamodule Revision ID Register (address location: 0181 2000h) See Section 5.3.6
JTAG BSDL_ID JTAGID register (address location: 0288 0818h) See Section 5.5.5
Frequency MHz 850 and 1000 (1 GHz)
Cycle Time ns 1.18 ns, 1 ns, and 0.83 ns (0.85- and 1-GHz CPU)
Voltage Core (V) 850-MHz CPU 1.1 V
1-GHz CPU 1.1 V
I/O (V) 850-MHz CPU 1.1 V, 1.8 V, and 3.3 V
1-GHz CPU 1.1 V, 1.8 V, and 3.3 V
PLL1 and PLL1 Controller Options CLKIN1 frequency multiplier Bypass (×1), (×4 to ×32)
PLL2 DDR2 Clock ×10
BGA Package 23 mm × 23 mm 688-Pin Flip-Chip Plastic BGA (GMH)
Process Technology µm 0.065 µm
Product Status Production Data (PD) PD
Device Part Numbers (For more details on the C64x+™ DSP part numbering, see Figure 6-1) SM320C6457CGMHS

5.2 CPU (DSP Core) Description

The C64x+ Central Processing Unit (CPU) consists of eight functional units, two register files, and two data paths as shown in Figure 2-1. The two general-purpose register files (A and B) each contain 32 32-bit registers for a total of 64 registers. The general-purpose registers can be used for data or can be data address pointers. The data types supported include packed 8-bit data, packed 16-bit data, 32-bit data, 40-bit data, and 64-bit data. Values larger than 32 bits, such as 40-bit-long or 64-bit-long values are stored in register pairs, with the 32 LSBs of data placed in an even register and the remaining 8 or 32 MSBs in the next upper register (which is always an odd-numbered register).

The eight functional units (.M1, .L1, .D1, .S1, .M2, .L2, .D2, and .S2) are each capable of executing one instruction every clock cycle. The .M functional units perform all multiply operations. The .S and .L units perform a general set of arithmetic, logical, and branch functions. The .D units primarily load data from memory to the register file and store results from the register file into memory.

The C64x+ CPU extends the performance of the C64x core through enhancements and new features.

Each C64x+ .M unit can perform one of the following each clock cycle: one 32 × 32 bit multiply, two 16 × 16 bit multiplies, two 16 × 32 bit multiplies, four 8 × 8 bit multiplies, four 8 × 8 bit multiplies with add operations, and four 16 × 16 multiplies with add/subtract capabilities (including a complex multiply). There is also support for Galois field multiplication for 8-bit and 32-bit data. Many communications algorithms such as FFTs and modems require complex multiplication. The complex multiply (CMPY) instruction takes four 16-bit inputs and produces a 32-bit real and a 32-bit imaginary output. There are also complex multiplies with rounding capability that produces one 32-bit packed output that contain 16-bit real and 16-bit imaginary values. The 32 × 32 bit multiply instructions provide the extended precision necessary for audio and other high-precision algorithms on a variety of signed and unsigned 32-bit data types.

The .L or (Arithmetic Logic Unit) now incorporates the ability to do parallel add/subtract operations on a pair of common inputs. Versions of this instruction exist to work on 32-bit data or on pairs of 16-bit data performing dual 16-bit add and subtracts in parallel. There are also saturated forms of these instructions. The C64x+ core enhances the .S unit in several ways. In the C64x core, dual 16-bit MIN2 and MAX2 comparisons were only available on the .L units. On the C64x+ core they are also available on the .S unit which increases the performance of algorithms that do searching and sorting. Finally, to increase data packing and unpacking throughput, the .S unit allows sustained high performance for the quad 8-bit/16-bit and dual 16-bit instructions. Unpack instructions prepare 8-bit data for parallel 16-bit operations. Pack instructions return parallel results to output precision including saturation support.

Other new features include:

  • SPLOOP — A small instruction buffer in the CPU that aids in creation of software pipelining loops where multiple iterations of a loop are executed in parallel. The SPLOOP buffer reduces the code size associated with software pipelining. Furthermore, loops in the SPLOOP buffer are fully interruptible.
  • Compact Instructions — The native instruction size for the C6000 devices is 32 bits. Many common instructions such as MPY, AND, OR, ADD, and SUB can be expressed as 16 bits if the C64x+ compiler can restrict the code to use certain registers in the register file. This compression is performed by the code generation tools.
  • Instruction Set Enhancements — As noted above, there are new instructions such as 32-bit multiplications, complex multiplications, packing, sorting, bit manipulation, and 32-bit Galois field multiplication.
  • Exception Handling — Intended to aid the programmer in isolating bugs. The C64x+ CPU is able to detect and respond to exceptions, both from internally detected sources (such as illegal op-codes) and from system events (such as a watchdog time expiration).
  • Privilege — Defines user and supervisor modes of operation, allowing the operating system to give a basic level of protection to sensitive resources. Local memory is divided into multiple pages, each with read, write, and execute permissions.
  • Time-Stamp Counter — Primarily targeted for Real-Time Operating System (RTOS) robustness, a free-running time-stamp counter is implemented in the CPU, which is not sensitive to system stalls.

For more details on the C64x+ CPU and its enhancements over the C64x architecture, see the following documents:

  • TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide (SPRU732)
  • TMS320C64x+ DSP Cache User's Guide (SPRU862)
  • TMS320C64x+ Megamodule Reference Guide (SPRU871)
  • TMS320C64x to TMS320C64x+ CPU Migration Guide (SPRAA84)

Figure 5-1 shows the DSP core functional units and data paths.

SM320C6457-HIREL C64x_plus_CPU_DSP_Core.gif Figure 5-1 TMS320C64x+ CPU (DSP Core) Data Paths
(A) On .M unit, dst2 is 32 MSB. ____(B) On .M unit, dst1 is 32 LSB. ____(C) On C64x CPU .M unit, src2 is 32 bits; on C64x+ CPU .M unit, src2 is 64 bits. (D) On .L and .S units, odd dst connects to odd register files and even dst connects to even register files.

5.3 C64x+ Megamodule

The C64x+ Megamodule consists of several components:

  • The C64x+ CPU and associated C64x+ Megamodule core
  • Level-one and level-two memories (L1P, L1D, L2)
  • Interrupt controller
  • Power-down controller
  • External memory controller
  • A dedicated power/sleep controller (LPSC)

The C64x+ Megamodule also provides support for memory protection and bandwidth management (for resources local to the C64x+ Megamodule). Figure 5-2 shows a block diagram of the C64x+ Megamodule.

SM320C6457-HIREL megamodule_block_diagram_f1.gif Figure 5-2 64x+ Megamodule Block Diagram

For more detailed information on the TMS320C64x+ megamodule on the C6457 device, see the TMS320C64x+ Megamodule Reference Guide (SPRU871).

5.3.1 Memory Architecture

The C6457 device contains a 2048KB level-2 memory (L2), a 32KB level-1 program memory (L1P), and a 32KB level-1 data memory (L1D). All memory on the C6457 has a unique location in the memory map (see Table 5-14).

After device reset, L1P and L1D cache are configured as all cache, by default. The L1P and L1D cache can be reconfigured via software through the L1PMODE field of the L1P Configuration Register (L1PMODE) and the L1DMODE field of the L1D Configuration Register (L1DCFG) of the C64x+ Megamodule. L1D is a two-way set-associative cache, while L1P is a direct-mapped cache.

The on-chip bootloader changes the reset configuration for L1P and L1D. For more information, see the TMS320C6457 Bootloader User's Guide (SPRUGL5).

For more information on the operation L1 and L2 caches, see the TMS320C64x+ DSP Cache User's Guide (SPRU862).

5.3.1.1 L1P Memory

The L1P memory configuration for the C6457 device is as follows:

  • Region 0 size is 0K bytes (disabled)
  • Region 1 size is 32K bytes with no wait states

Figure 5-3 shows the available SRAM/cache configurations for L1P.

SM320C6457-HIREL L1P_Memory_Configurations_6484.gif Figure 5-3 C6457 L1P Memory Configurations

5.3.1.2 L1D Memory

The L1D memory configuration for the C6457 device is as follows:

  • Region 0 size is 0K bytes (disabled)
  • Region 1 size is 32K bytes with no wait states

Figure 5-4 shows the available SRAM/cache configurations for L1D.

SM320C6457-HIREL L1D_memory_f1.gif Figure 5-4 C6457 L1D Memory Configurations

5.3.1.3 L2 Memory

The L2 memory configuration for the C6457 device is as follows:

  • Memory size is 2048KB
  • Starting address is 0080 0000h

L2 memory can be configured as all SRAM or as part 4-way set-associative cache. The amount of L2 memory that is configured as cache is controlled through the L2MODE field of the L2 Configuration Register (L2CFG) of the C64x+ Megamodule. Figure 5-5 shows the available SRAM/cache configurations for L2. By default, L2 is configured as all SRAM after device reset.

SM320C6457-HIREL L2_Memory_Configurations_6484.gif Figure 5-5 C6457 L2 Memory Configurations

5.3.1.4 L3 Memory

The L3 ROM on the device is 64KB. The contents of the ROM are divided into two partitions. The first is the ROM bootloader with the primary purpose of containing software to boot the device. There is no requirement to block accesses from this portion to the ROM. The second partition is the secure portion of ROM, which has a secure kernel that is necessary for support of security features on the device. The secure portion of ROM cannot be accessed both on secure, and non-secure parts. Only secure supervisors should have access.

Emulation accesses follows the same rules of the secure portion of the ROM. Emulation can access the non-secure portion of the ROM, but cannot read the secure portion of the ROM.

5.3.2 Memory Protection

Memory protection allows an operating system to define who or what is authorized to access L1D, L1P, and L2 memory. To accomplish this, the L1D, L1P, and L2 memories are divided into pages. There are 16 pages of L1P (2KB each), 16 pages of L1D (2KB each), and 64 pages of L2 (32KB each). The L1D, L1P, and L2 memory controllers in the C64x+ Megamodule are equipped with a set of registers that specify the permissions for each memory page.

Each page may be assigned with fully orthogonal user and supervisor read, write, and execute permissions. In addition, a page may be marked as either (or both) locally accessible or globally accessible. A local access is a direct CPU access to L1D, L1P, and L2, while a global access is initiated by a DMA (either IDMA or the EDMA3) or by other system masters. Note that EDMA or IDMA transfers programmed by the CPU count as global accesses. On a secure device, pages can be restricted to secure access only (default) or opened up for public, non-secure access.

The CPU and each of the system masters on the device are all assigned a privilege ID (see Table 5-2). It is only possible to specify whether memory pages are locally or globally accessible.

Table 5-2 Available Memory Page Protection Scheme With Privilege ID

PRIVID MODULE DESCRIPTION
0 C64x+ Megamodule
1 Reserved
2 Reserved
3 EMAC
4 RapidIO and RapidIO CPPI
5 HPI

The AID0 and LOCAL bits of the memory protection page attribute registers specify the memory page protection scheme, see Table 5-3.

Table 5-3 Available Memory Page Protection Schemes

AID0 BIT LOCAL BIT DESCRIPTION
0 0 No access to memory page is permitted.
0 1 Only direct access by CPU is permitted.
1 0 Only accesses by system masters and IDMA are permitted (includes EDMA and IDMA accesses initiated by the CPU).
1 1 All accesses permitted

Faults are handled by software in an interrupt (or an exception, programmable within the C64x+ megamodule interrupt controller) service routine. A CPU or DMA access to a page without the proper permissions will:

  • Block the access — reads return zero, writes are ignored
  • Capture the initiator in a status register — ID, address, and access type are stored
  • Signal event to CPU interrupt controller

The software is responsible for taking corrective action to respond to the event and resetting the error status in the memory controller. For more information on memory protection for L1D, L1P, and L2, see the TMS320C64x+ Megamodule Reference Guide (SPRU871).

5.3.3 Bandwidth Management

When multiple requestors contend for a single C64x+ Megamodule resource, the conflict is resolved by granting access to the highest priority requestor. The following four resources are managed by the Bandwidth Management control hardware:

  • Level 1 Program (L1P) SRAM/Cache
  • Level 1 Data (L1D) SRAM/Cache
  • Level 2 (L2) SRAM/Cache
  • Memory-mapped registers configuration bus

The priority level for operations initiated within the C64x+ Megamodule are declared through registers in the C64x+ Megamodule. These operations are:

  • CPU-initiated transfers
  • User-programmed cache coherency operations
  • IDMA-initiated transfers

The priority level for operations initiated outside the C64x+ Megamodule by system peripherals is declared through the Priority Allocation Register (PRI_ALLOC), see Section 5.6.4. System peripherals with no fields in PRI_ALLOC have their own registers to program their priorities.

More information on the bandwidth management features of the C64x+ Megamodule can be found in the TMS320C64x+ Megamodule Reference Guide (SPRU871).

5.3.4 Power-Down Control

The C64x+ Megamodule supports the ability to power-down various parts of the C64x+ Megamodule. The power-down controller (PDC) of the C64x+ Megamodule can be used to power down L1P, the cache control hardware, the CPU, and the entire C64x+ Megamodule. These power-down features can be used to design systems for lower overall system power requirements.

NOTE

The C6457 does not support power-down modes for the L2 memory at this time.

More information on the power-down features of the C64x+ Megamodule can be found in the TMS320C64x+ Megamodule Reference Guide (SPRU871).

5.3.5 Megamodule Resets

Table 5-4 shows the reset types supported on the C6457 device and they affect the resetting of the Megamodule, either both globally or just locally.

Table 5-4 Megamodule Reset (Global or Local)

RESET TYPE GLOBAL MEGAMODULE RESET LOCAL MEGAMODULE RESET
Power-On Reset Y Y
Warm Reset Y Y
System Reset Y Y
CPU Reset N Y

For more detailed information on the global and local Megamodule resets, see the TMS320C64x+ Megamodule Reference Guide (SPRU871). And for more detailed information on device resets, see Section 4.7.3.

5.3.6 Megamodule Revision

The version and revision of the C64x+ Megamodule can be read from the Megamodule Revision ID Register (MM_REVID) located at address 0181 2000h. The MM_REVID register is shown in Figure 5-6 and described in Table 5-5. The C64x+ Megamodule revision is dependant on the silicon revision being used.

Figure 5-6 Megamodule Revision ID Register (MM_REVID) (Address - 0181 2000h)(3)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
VERSION
R-5h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REVISION
R-n
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 5-5 Megamodule Revision ID Register (MM_REVID) Field Descriptions

Bit Acronym Value Description
31:16 VERSION 5h Version of the C64x+ Megamodule implemented on the device. This field is always read as 5h.
15:0 REVISION - Revision of the C64x+ Megamodule version implemented on the device.

5.3.7 C64x+ Megamodule Register Descriptions

Table 5-6 Megamodule Interrupt Registers

HEX ADDRESS RANGE ACRONYM REGISTER NAME
0180 0000 EVTFLAG0 Event Flag Register 0 (Events [31:0])
0180 0004 EVTFLAG1 Event Flag Register 1
0180 0008 EVTFLAG2 Event Flag Register 2
0180 000C EVTFLAG3 Event Flag Register 3
0180 0010 - 0180 001C - Reserved
0180 0020 EVTSET0 Event Set Register 0 (Events [31:0])
0180 0024 EVTSET1 Event Set Register 1
0180 0028 EVTSET2 Event Set Register 2
0180 002C EVTSET3 Event Set Register 3
0180 0030 - 0180 003C - Reserved
0180 0040 EVTCLR0 Event Clear Register 0 (Events [31:0])
0180 0044 EVTCLR1 Event Clear Register 1
0180 0048 EVTCLR2 Event Clear Register 2
0180 004C EVTCLR3 Event Clear Register 3
0180 0050 - 0180 007C - Reserved
0180 0080 EVTMASK0 Event Mask Register 0 (Events [31:0])
0180 0084 EVTMASK1 Event Mask Register 1
0180 0088 EVTMASK2 Event Mask Register 2
0180 008C EVTMASK3 Event Mask Register 3
0180 0090 - 0180 009C - Reserved
0180 00A0 MEVTFLAG0 Masked Event Flag Status Register 0 (Events [31:0])
0180 00A4 MEVTFLAG1 Masked Event Flag Status Register 1
0180 00A8 MEVTFLAG2 Masked Event Flag Status Register 2
0180 00AC MEVTFLAG3 Masked Event Flag Status Register 3
0180 00B0 - 0180 00BC - Reserved
0180 00C0 EXPMASK0 Exception Mask Register 0 (Events [31:0])
0180 00C4 EXPMASK1 Exception Mask Register 1
0180 00C8 EXPMASK2 Exception Mask Register 2
0180 00CC EXPMASK3 Exception Mask Register 3
0180 00D0 - 0180 00DC - Reserved
0180 00E0 MEXPFLAG0 Masked Exception Flag Register 0
0180 00E4 MEXPFLAG1 Masked Exception Flag Register 1
0180 00E8 MEXPFLAG2 Masked Exception Flag Register 2
0180 00EC MEXPFLAG3 Masked Exception Flag Register 3
0180 00F0 - 0180 00FC - Reserved
0180 0100 - Reserved
0180 0104 INTMUX1 Interrupt Multiplexor Register 1
0180 0108 INTMUX2 Interrupt Multiplexor Register 2
0180 010C INTMUX3 Interrupt Multiplexor Register 3
0180 0110 - 0180 013C - Reserved
0180 0140 AEGMUX0 Advanced Event Generator Mux Register 0
0180 0144 AEGMUX1 Advanced Event Generator Mux Register 1
0180 0148 - 0180 017C - Reserved
0180 0180 INTXSTAT Interrupt Exception Status Register
0180 0184 INTXCLR Interrupt Exception Clear Register
0180 0188 INTDMASK Dropped Interrupt Mask Register
0180 0188 - 0180 01BC - Reserved
0180 01C0 EVTASRT Event Asserting Register
0180 01C4 - 0180 FFFF - Reserved

Table 5-7 Megamodule Powerdown Control Registers

HEX ADDRESS RANGE ACRONYM REGISTER NAME
0181 0000 PDCCMD Power-down controller command register
0181 0004 - 0181 1FFF - Reserved

Table 5-8 Megamodule Revision Register

HEX ADDRESS RANGE ACRONYM REGISTER NAME
0181 2000 MM_REVID Megamodule Revision ID Register
0181 2004 - 0181 2FFF - Reserved

Table 5-9 Megamodule IDMA Registers

HEX ADDRESS RANGE ACRONYM REGISTER NAME
0182 0000 IDMA0STAT IDMA Channel 0 Status Register
0182 0004 IDMA0MASK IDMA Channel 0 Mask Register
0182 0008 IMDA0SRC IDMA Channel 0 Source Address Register
0182 000C IDMA0DST IDMA Channel 0 Destination Address Register
0182 0010 IDMA0CNT IDMA Channel 0 Count Register
0182 0014 - 0182 00FC - Reserved
0182 0100 IDMA1STAT IDMA Channel 1 Status Register
0182 0104 - Reserved
0182 0108 IMDA1SRC IDMA Channel 1 Source Address Register
0182 010C IDMA1DST IDMA Channel 1 Destination Address Register
0182 0110 IDMA1CNT IDMA Channel 1 Count Register
0182 0114 - 0182 017C - Reserved
0182 0180 - Reserved
0182 0184 - 0182 01FF - Reserved

Table 5-10 Megamodule Cache Configuration Registers

HEX ADDRESS RANGE ACRONYM REGISTER NAME
0184 0000 L2CFG L2 Cache Configuration Register
0184 0004 - 0184 001F - Reserved
0184 0020 L1PCFG L1P Configuration Register
0184 0024 L1PCC L1P Cache Control Register
0184 0028 - 0184 003F - Reserved
0184 0040 L1DCFG L1D Configuration Register
0184 0044 L1DCC L1D Cache Control Register
0184 0048 - 0184 0FFF - Reserved
0184 1000 - 0184 104F - See Table 5-13
0184 1050 - 0184 3FFF - Reserved
0184 4000 L2WBAR L2 Writeback Base Address Register — for Block Writebacks
0184 4004 L2WWC L2 Writeback Word Count Register
0184 4008 - 0184 400C - Reserved
0184 4010 L2WIBAR L2 Writeback and Invalidate Base Address Register — for Block Writebacks
0184 4014 L2WIWC L2 Writeback and Invalidate word count register
0184 4018 L2IBAR L2 Invalidate Base Address Register
0184 401C L2IWC L2 Invalidate Word Count Register
0184 4020 L1PIBAR L1P Invalidate Base Address Register
0184 4024 L1PIWC L1P Invalidate Word Count Register
0184 4030 L1DWIBAR L1D Writeback and Invalidate Base Address Register
0184 4034 L1DWIWC L1D Writeback and Invalidate Word Count Register
0184 4038 - Reserved
0184 4040 L1DWBAR L1D Writeback Base Address Register — for Block Writebacks
0184 4044 L1DWWC L1D Writeback Word Count Register
0184 4048 L1DIBAR L1D Invalidate Base Address Register
0184 404C L1DIWC L1D Invalidate Word Count Register
0184 4050 - 0184 4FFF - Reserved
0184 5000 L2WB L2 Global Writeback Register
0184 5004 L2WBINV L2 Global Writeback and Invalidate Register
0184 5008 L2INV L2 Global Invalidate Register
0184 500C - 0184 5024 - Reserved
0184 5028 L1PINV L1P Global Invalidate Register
0184 502C - 0184 503C - Reserved
0184 5040 L1DWB L1D Global Writeback Register
0184 5044 L1DWBINV L1D Global Writeback and Invalidate Register
0184 5048 L1DINV L1D Global Invalidate Register
0184 504C - 0184 5FFF - Reserved
0184 6000 - 0184 640F - See Table 5-11
0184 6410 - 0184 7FFF - Reserved
0184 8000 - 0184 81FC MAR0 to MAR127 Reserved
0184 8200 - 0184 823C MAR128 to MAR143 Reserved
0184 8240 - 0184 827C MAR144 to MAR159 Reserved
0184 8280 MAR160 Controls EMIFA CE2 Range A000 0000 - A0FF FFFF
0184 8284 MAR161 Controls EMIFA CE2 Range A100 0000 - A1FF FFFF
0184 8288 MAR162 Controls EMIFA CE2 Range A200 0000 - A2FF FFFF
0184 828C MAR163 Controls EMIFA CE2 Range A300 0000 - A3FF FFFF
0184 8290 MAR164 Controls EMIFA CE2 Range A400 0000 - A4FF FFFF
0184 8294 MAR165 Controls EMIFA CE2 Range A500 0000 - A5FF FFFF
0184 8298 MAR166 Controls EMIFA CE2 Range A600 0000 - A6FF FFFF
0184 829C MAR167 Controls EMIFA CE2 Range A700 0000 - A7FF FFFF
0184 82A0 MAR168 Controls EMIFA CE2 Range A800 0000 - A8FF FFFF
0184 82A4 MAR169 Controls EMIFA CE2 Range A900 0000 - A9FF FFFF
0184 82A8 MAR170 Controls EMIFA CE2 Range AA00 0000 - AAFF FFFF
0184 82AC MAR171 Controls EMIFA CE2 Range AB00 0000 - ABFF FFFF
0184 82B0 MAR172 Controls EMIFA CE2 Range AC00 0000 - ACFF FFFF
0184 82B4 MAR173 Controls EMIFA CE2 Range AD00 0000 - ADFF FFFF
0184 82B8 MAR174 Controls EMIFA CE2 Range AE00 0000 - AEFF FFFF
0184 82BC MAR175 Controls EMIFA CE2 Range AF00 0000 - AFFF FFFF
0184 82C0 MAR176 Controls EMIFA CE3 Range B000 0000 - B0FF FFFF
0184 82C4 MAR177 Controls EMIFA CE3 Range B100 0000 - B1FF FFFF
0184 82C8 MAR178 Controls EMIFA CE3 Range B200 0000 - B2FF FFFF
0184 82CC MAR179 Controls EMIFA CE3 Range B300 0000 - B3FF FFFF
0184 82D0 MAR180 Controls EMIFA CE3 Range B400 0000 - B4FF FFFF
0184 82D4 MAR181 Controls EMIFA CE3 Range B500 0000 - B5FF FFFF
0184 82D8 MAR182 Controls EMIFA CE3 Range B600 0000 - B6FF FFFF
0184 82DC MAR183 Controls EMIFA CE3 Range B700 0000 - B7FF FFFF
0184 82E0 MAR184 Controls EMIFA CE3 Range B800 0000 - B8FF FFFF
0184 82E4 MAR185 Controls EMIFA CE3 Range B900 0000 - B9FF FFFF
0184 82E8 MAR186 Controls EMIFA CE3 Range BA00 0000 - BAFF FFFF
0184 82EC MAR187 Controls EMIFA CE3 Range BB00 0000 - BBFF FFFF
0184 82F0 MAR188 Controls EMIFA CE3 Range BC00 0000 - BCFF FFFF
0184 82F4 MAR189 Controls EMIFA CE3 Range BD00 0000 - BDFF FFFF
0184 82F8 MAR190 Controls EMIFA CE3 Range BE00 0000 - BEFF FFFF
0184 82FC MAR191 Controls EMIFA CE3 Range BF00 0000 - BFFF FFFF
0184 8300 MAR192 Controls EMIFA CE4 Range C000 0000 - C0FF FFFF
0184 8304 MAR193 Controls EMIFA CE4 Range C100 0000 - C1FF FFFF
0184 8308 MAR194 Controls EMIFA CE4 Range C200 0000 - C2FF FFFF
0184 830C MAR195 Controls EMIFA CE4 Range C300 0000 - C3FF FFFF
0184 8310 MAR196 Controls EMIFA CE4 Range C400 0000 - C4FF FFFF
0184 8314 MAR197 Controls EMIFA CE4 Range C500 0000 - C5FF FFFF
0184 8318 MAR198 Controls EMIFA CE4 Range C600 0000 - C6FF FFFF
0184 831C MAR199 Controls EMIFA CE4 Range C700 0000 - C7FF FFFF
0184 8320 MAR200 Controls EMIFA CE4 Range C800 0000 - C8FF FFFF
0184 8324 MAR201 Controls EMIFA CE4 Range C900 0000 - C9FF FFFF
0184 8328 MAR202 Controls EMIFA CE4 Range CA00 0000 - CAFF FFFF
0184 832C MAR203 Controls EMIFA CE4 Range CB00 0000 - CBFF FFFF
0184 8330 MAR204 Controls EMIFA CE4 Range CC00 0000 - CCFF FFFF
0184 8334 MAR205 Controls EMIFA CE4 Range CD00 0000 - CDFF FFFF
0184 8338 MAR206 Controls EMIFA CE4 Range CE00 0000 - CEFF FFFF
0184 833C MAR207 Controls EMIFA CE4 Range CF00 0000 - CFFF FFFF
0184 8340 MAR208 Controls EMIFA CE5 Range D000 0000 - D0FF FFFF
0184 8344 MAR209 Controls EMIFA CE5 Range D100 0000 - D1FF FFFF
0184 8348 MAR210 Controls EMIFA CE5 Range D200 0000 - D2FF FFFF
0184 834C MAR211 Controls EMIFA CE5 Range D300 0000 - D3FF FFFF
0184 8350 MAR212 Controls EMIFA CE5 Range D400 0000 - D4FF FFFF
0184 8354 MAR213 Controls EMIFA CE5 Range D500 0000 - D5FF FFFF
0184 8358 MAR214 Controls EMIFA CE5 Range D600 0000 - D6FF FFFF
0184 835C MAR215 Controls EMIFA CE5 Range D700 0000 - D7FF FFFF
0184 8360 MAR216 Controls EMIFA CE5 Range D800 0000 - D8FF FFFF
0184 8364 MAR217 Controls EMIFA CE5 Range D900 0000 - D9FF FFFF
0184 8368 MAR218 Controls EMIFA CE5 Range DA00 0000 - DAFF FFFF
0184 836C MAR219 Controls EMIFA CE5 Range DB00 0000 - DBFF FFFF
0184 8370 MAR220 Controls EMIFA CE5 Range DC00 0000 - DCFF FFFF
0184 8374 MAR221 Controls EMIFA CE5 Range DD00 0000 - DDFF FFFF
0184 8378 MAR222 Controls EMIFA CE5 Range DE00 0000 - DEFF FFFF
0184 837C MAR223 Controls EMIFA CE5 Range DF00 0000 - DFFF FFFF
0184 8380 MAR224 Controls DDR2 CE0 Range E000 0000 - E0FF FFFF
0184 8384 MAR225 Controls DDR2 CE0 Range E100 0000 - E1FF FFFF
0184 8388 MAR226 Controls DDR2 CE0 Range E200 0000 - E2FF FFFF
0184 838C MAR227 Controls DDR2 CE0 Range E300 0000 - E3FF FFFF
0184 8390 MAR228 Controls DDR2 CE0 Range E400 0000 - E4FF FFFF
0184 8394 MAR229 Controls DDR2 CE0 Range E500 0000 - E5FF FFFF
0184 8398 MAR230 Controls DDR2 CE0 Range E600 0000 - E6FF FFFF
0184 839C MAR231 Controls DDR2 CE0 Range E700 0000 - E7FF FFFF
0184 83A0 MAR232 Controls DDR2 CE0 Range E800 0000 - E8FF FFFF
0184 83A4 MAR233 Controls DDR2 CE0 Range E900 0000 - E9FF FFFF
0184 83A8 MAR234 Controls DDR2 CE0 Range EA00 0000 - EAFF FFFF
0184 83AC MAR235 Controls DDR2 CE0 Range EB00 0000 - EBFF FFFF
0184 83B0 MAR236 Controls DDR2 CE0 Range EC00 0000 - ECFF FFFF
0184 83B4 MAR237 Controls DDR2 CE0 Range ED00 0000 - EDFF FFFF
0184 83B8 MAR238 Controls DDR2 CE0 Range EE00 0000 - EEFF FFFF
0184 83BC MAR239 Controls DDR2 CE0 Range EF00 0000 - EFFF FFFF
0184 83C0 - 0184 83FC MAR240 to MAR255 Reserved

Table 5-11 Megamodule Error Detection Correct Registers

HEX ADDRESS RANGE ACRONYM REGISTER NAME
0184 6000 - Reserved
0184 6004 L2EDSTAT L2 Error Detection Status Register
0184 6008 L2EDCMD L2 Error Detection Command Register
0184 600C L2EDADDR L2 Error Detection Address Register
0184 6010 L2EDEN0 L2 Error Detection Enable Map 0 Register
0184 6014 L2EDEN1 L2 Error Detection Enable Map 1 Register
0184 6018 L2EDCPEC L2 Error Detection — Correctable Parity Error Count Register
0184 601C L2EDNPEC L2 Error Detection — Non-Correctable Parity Error Count Register
0184 6020 - 0184 6400 - Reserved
0184 6404 L1PEDSTAT L1P Error Detection Status Register
0184 6408 L1PEDCMD L1P Error Detection Command Register
0184 640C L1PEDADDR L1P Error Detection Address Register

Table 5-12 Megamodule L1/L2 Memory Protection Registers

HEX ADDRESS RANGE ACRONYM REGISTER NAME
0184 A000 L2MPFAR L2 memory protection fault address register
0184 A004 L2MPFSR L2 memory protection fault status register
0184 A008 L2MPFCR L2 memory protection fault command register
0184 A00C - 0184 A0FF - Reserved
0184 A100 L2MPLK0 L2 memory protection lock key bits [31:0]
0184 A104 L2MPLK1 L2 memory protection lock key bits [63:32]
0184 A108 L2MPLK2 L2 memory protection lock key bits [95:64]
0184 A10C L2MPLK3 L2 memory protection lock key bits [127:96]
0184 A110 L2MPLKCMD L2 memory protection lock key command register
0184 A114 L2MPLKSTAT L2 memory protection lock key status register
0184 A118 - 0184 A1FF - Reserved
0184 A200 L2MPPA0 L2 memory protection page attribute register 0
0184 A204 L2MPPA1 L2 memory protection page attribute register 1
0184 A208 L2MPPA2 L2 memory protection page attribute register 2
0184 A20C L2MPPA3 L2 memory protection page attribute register 3
0184 A210 L2MPPA4 L2 memory protection page attribute register 4
0184 A214 L2MPPA5 L2 memory protection page attribute register 5
0184 A218 L2MPPA6 L2 memory protection page attribute register 6
0184 A21C L2MPPA7 L2 memory protection page attribute register 7
0184 A220 L2MPPA8 L2 memory protection page attribute register 8
0184 A224 L2MPPA9 L2 memory protection page attribute register 9
0184 A228 L2MPPA10 L2 memory protection page attribute register 10
0184 A22C L2MPPA11 L2 memory protection page attribute register 11
0184 A230 L2MPPA12 L2 memory protection page attribute register 12
0184 A234 L2MPPA13 L2 memory protection page attribute register 13
0184 A238 L2MPPA14 L2 memory protection page attribute register 14
0184 A23C L2MPPA15 L2 memory protection page attribute register 15
0184 A240 L2MPPA16 L2 memory protection page attribute register 16
0184 A244 L2MPPA17 L2 memory protection page attribute register 17
0184 A248 L2MPPA18 L2 memory protection page attribute register 18
0184 A24C L2MPPA19 L2 memory protection page attribute register 19
0184 A250 L2MPPA20 L2 memory protection page attribute register 20
0184 A254 L2MPPA21 L2 memory protection page attribute register 21
0184 A258 L2MPPA22 L2 memory protection page attribute register 22
0184 A25C L2MPPA23 L2 memory protection page attribute register 23
0184 A260 L2MPPA24 L2 memory protection page attribute register 24
0184 A264 L2MPPA25 L2 memory protection page attribute register 25
0184 A268 L2MPPA26 L2 memory protection page attribute register 26
0184 A26C L2MPPA27 L2 memory protection page attribute register 27
0184 A270 L2MPPA28 L2 memory protection page attribute register 28
0184 A274 L2MPPA29 L2 memory protection page attribute register 29
0184 A278 L2MPPA30 L2 memory protection page attribute register 30
0184 A27C L2MPPA31 L2 memory protection page attribute register 31
0184 A280 - 0184 A2FC(1) - Reserved
0184 0300 - 0184 A3FF - Reserved
0184 A400 L1PMPFAR L1 program (L1P) memory protection fault address register
0184 A404 L1PMPFSR L1P memory protection fault status register
0184 A408 L1PMPFCR L1P memory protection fault command register
0184 A40C - 0184 A4FF - Reserved
0184 A500 L1PMPLK0 L1P memory protection lock key bits [31:0]
0184 A504 L1PMPLK1 L1P memory protection lock key bits [63:32]
0184 A508 L1PMPLK2 L1P memory protection lock key bits [95:64]
0184 A50C L1PMPLK3 L1P memory protection lock key bits [127:96]
0184 A510 L1PMPLKCMD L1P memory protection lock key command register
0184 A514 L1PMPLKSTAT L1P memory protection lock key status register
0184 A518 - 0184 A5FF - Reserved
0184 A600 - 0184 A63C(1) - Reserved
0184 A640 L1PMPPA16 L1P memory protection page attribute register 16
0184 A644 L1PMPPA17 L1P memory protection page attribute register 17
0184 A648 L1PMPPA18 L1P memory protection page attribute register 18
0184 A64C L1PMPPA19 L1P memory protection page attribute register 19
0184 A650 L1PMPPA20 L1P memory protection page attribute register 20
0184 A654 L1PMPPA21 L1P memory protection page attribute register 21
0184 A658 L1PMPPA22 L1P memory protection page attribute register 22
0184 A65C L1PMPPA23 L1P memory protection page attribute register 23
0184 A660 L1PMPPA24 L1P memory protection page attribute register 24
0184 A664 L1PMPPA25 L1P memory protection page attribute register 25
0184 A668 L1PMPPA26 L1P memory protection page attribute register 26
0184 A66C L1PMPPA27 L1P memory protection page attribute register 27
0184 A670 L1PMPPA28 L1P memory protection page attribute register 28
0184 A674 L1PMPPA29 L1P memory protection page attribute register 29
0184 A678 L1PMPPA30 L1P memory protection page attribute register 30
0184 A67C L1PMPPA31 L1P memory protection page attribute register 31
0184 A680 - 0184 ABFF - Reserved
0184 AC00 L1DMPFAR L1 data (L1D) memory protection fault address register
0184 AC04 L1DMPFSR L1D memory protection fault status register
0184 AC08 L1DMPFCR L1D memory protection fault command register
0184 AC0C - 0184 ACFF - Reserved
0184 AD00 L1DMPLK0 L1D memory protection lock key bits [31:0]
0184 AD04 L1DMPLK1 L1D memory protection lock key bits [63:32]
0184 AD08 L1DMPLK2 L1D memory protection lock key bits [95:64]
0184 AD0C L1DMPLK3 L1D memory protection lock key bits [127:96]
0184 AD10 L1DMPLKCMD L1D memory protection lock key command register
0184 AD14 L1DMPLKSTAT L1D memory protection lock key status register
0184 AD18 - 0184 ADFF - Reserved
0184 AE00 - 0184 AE3C(2) - Reserved
0184 AE40 L1DMPPA16 L1D memory protection page attribute register 16
0184 AE44 L1DMPPA17 L1D memory protection page attribute register 17
0184 AE48 L1DMPPA18 L1D memory protection page attribute register 18
0184 AE4C L1DMPPA19 L1D memory protection page attribute register 19
0184 AE50 L1DMPPA20 L1D memory protection page attribute register 20
0184 AE54 L1DMPPA21 L1D memory protection page attribute register 21
0184 AE58 L1DMPPA22 L1D memory protection page attribute register 22
0184 AE5C L1DMPPA23 L1D memory protection page attribute register 23
0184 AE60 L1DMPPA24 L1D memory protection page attribute register 24
0184 AE64 L1DMPPA25 L1D memory protection page attribute register 25
0184 AE68 L1DMPPA26 L1D memory protection page attribute register 26
0184 AE6C L1DMPPA27 L1D memory protection page attribute register 27
0184 AE70 L1DMPPA28 L1D memory protection page attribute register 28
0184 AE74 L1DMPPA29 L1D memory protection page attribute register 29
0184 AE78 L1DMPPA30 L1D memory protection page attribute register 30
0184 AE7C L1DMPPA31 L1D memory protection page attribute register 31
0184 AE80 - 0185 FFFF - Reserved
(1) These addresses correspond to the L1P memory protection page attribute registers 0-15 (L1PMPPA0 - L1PMPPA15) of the C64x+ Megamodule. These registers are not supported for the C6457 device.
(2) These addresses correspond to the L1D memory protection page attribute registers 0-15 (L1DMPPA0 - L1DMPPA15) of the C64x+ Megamodule. These registers are not supported for the C6457 device.

Table 5-13 CPU Megamodule Bandwidth Management Registers

HEX ADDRESS RANGE ACRONYM REGISTER NAME
0182 0200 EMCCPUARBE EMC CPU Arbitration Control Register
0182 0204 EMCIDMAARBE EMC IDMA Arbitration Control Register
0182 0208 EMCSDMAARBE EMC Slave DMA Arbitration Control Register
0182 020C EMCMDMAARBE EMC Master DMA Arbitration Control Register
0182 0210 - 0182 02FF - Reserved
0184 1000 L2DCPUARBU L2D CPU Arbitration Control Register
0184 1004 L2DIDMAARBU L2D IDMA Arbitration Control Register
0184 1008 L2DSDMAARBU L2D Slave DMA Arbitration Control Register
0184 100C L2DUCARBU L2D User Coherence Arbitration Control Register
0184 1010 - 0184 103F - Reserved
0184 1040 L1DCPUARBD L1D CPU Arbitration Control Register
0184 1044 L1DIDMAARBD L1D IDMA Arbitration Control Register
0184 1048 L1DSDMAARBD L1D Slave DMA Arbitration Control Register
0184 104C L1DUCARBD L1D User Coherence Arbitration Control Register

5.4 Memory Map Summary

Table 5-14 shows the memory map address ranges of the SM320C6457-HIREL device. The external memory configuration register address ranges in the SM320C6457-HIREL device begin at the hex address location 0x7000 0000 for EMIFA and hex address location 0x7800 0000 for DDR2 Memory Controller.

Table 5-14 SM320C6457-HIREL Memory Map Summary

MEMORY BLOCK DESCRIPTION BLOCK SIZE (BYTES) HEX ADDRESS RANGE
Reserved 8M 0000 0000 - 007F FFFF
L2 SRAM 2M 0080 0000 - 009F FFFF
Reserved 4M 00A0 0000 - 00DF FFFF
L1P SRAM 32K 00E0 0000 - 00E0 7FFF
Reserved 1M - 32K 00E0 8000 - 00EF FFFF
L1D SRAM 32K 00F0 0000 - 00F0 7FFF
Reserved 1M -32K 00F0 8000 - 00FF FFFF
Reserved 8M 0100 0000 - 017F FFFF
C64x+ Megamodule Registers 4M 0180 0000 - 01BF FFFF
Reserved 12.5M 01C0 0000 - 0287 FFFF
HPI Control Registers 256 0288 0000 - 0288 00FF
Reserved 2K - 256 0288 0100 - 0288 07FF
Chip-Level Registers 1K 0288 0800 - 0288 0BFF
Reserved 253K 0288 0C00 - 028B FFFF
McBSP 0 Registers 256 028C 0000 - 028C 00FF
Reserved 256K - 256 028C 0100 - 028F FFFF
McBSP 1 Registers 256 0290 0000 - 0290 00FF
Reserved 256K - 256 0290 0100 - 0293 FFFF
Timer 0 Registers 128 0294 0000 - 0294 007F
Reserved 256K - 128 0294 0080 - 0297 FFFF
Timer 1 Registers 128 0298 0000 - 0298 007F
Reserved 128K - 128 0298 0080 - 0299 FFFF
PLL Controller (including Reset Controller) Registers 512 029A 0000 - 029A 01FF
Reserved 384K - 512 029A 0200 - 029F FFFF
EDMA3 Channel Controller Registers 32K 02A0 0000 - 02A0 7FFF
Reserved 96K 02A0 8000 - 02A1 FFFF
EDMA3 Transfer Controller 0 Registers 1K 02A2 0000 - 02A2 03FF
Reserved 31K 02A2 0400 - 02A2 7FFF
EDMA3 Transfer Controller 1 Registers 1K 02A2 8000 - 02A2 83FF
Reserved 31K 02A2 8400 - 02A2 FFFF
EDMA3 Transfer Controller 2 Registers 1K 02A3 0000 - 02A3 03FF
Reserved 31K 02A3 0400 - 02A3 7FFF
EDMA3 Transfer Controller 3 Registers 1K 02A3 8000 - 02A3 83FF
Reserved 31K 02A3 8400 - 02A3 FFFF
EDMA3 Transfer Controller 4 Registers 1K 02A4 0000 - 02A4 03FF
Reserved 31K 02A4 0400 - 02A4 7FFF
EDMA3 Transfer Controller 5 Registers 1K 02A4 8000 - 02A4 83FF
Reserved 479K 02A4 8400 - 02AB FFFF
Power / Sleep Controller (PSC) 4K 02AC 0000 - 02AC 0FFF
Reserved 60K 02AC 1000 - 02AC FFFF
Embedded Trace Buffer (ETB) 8K 02AD 0000 - 02AD 1FFF
Reserved 184K 02AD 2000 - 02AF FFFF
GPIO Registers 256 02B0 0000 - 02B0 00FF
Reserved 16K - 256 02B0 0100 - 02B0 3FFF
I2C Data and Control Registers 128 02B0 4000 - 02B0 407F
Reserved 240K - 128 02B0 4080 - 02B3 FFFF
UTOPIA Control Registers 512 02B4 0000 - 02B4 01FF
Reserved 256K - 512 02B4 0200 - 02B7 FFFF
VCP2 Control Registers 256 02B8 0000 - 02B8 00FF
Reserved 128K - 256 02B8 0100 - 02B9 FFFF
TCP2_A Control Registers 256 02BA 0000 - 02BA 00FF
TCP2_B Control Registers 256 02BA 0100 - 02BA 01FF
Reserved 640K - 512 02BA 0200 - 02C3 FFFF
SGMII Control 256 02C4 0000 - 02C4 00FF
Reserved 256K - 256 02C4 0100 - 02C7 FFFF
EMAC Control 2K 02C8 0000 - 02C8 07FF
Reserved 2K 02C8 0800 - 02C8 0FFF
EMAC Interrupt Controller 256 02C8 1000 - 02C8 10FF
Reserved 2K - 256 02C8 1100 - 02C8 17FF
MDIO Control Registers 256 02C8 1800 - 02C8 18FF
Reserved 2K - 256 02C8 1900 - 02C8 1FFF
EMAC Descriptor Memory 8K 02C8 2000 - 02C8 3FFF
Reserved 496K 02C8 4000 - 02CF FFFF
RapidIO Control Registers 132K 02D0 0000 - 02D2 0FFF
Reserved 892K 02D2 1000 - 02DF FFFF
RapidIO Descriptor Memory 16K 02E0 0000 - 02E0 3FFF
Reserved 1M - 16K 02E0 4000 - 02EF FFFF
Reserved 1M 02F0 0000 - 02FF FFFF
Reserved 208M 0300 0000 - 0FFF FFFF
Reserved 512M 1000 0000 - 2FFF FFFF
McBSP 0 Data 256 3000 0000 - 3000 00FF
Reserved 64M - 256 3000 0100 - 33FF FFFF
McBSP 1 Data 256 3400 0000 - 3400 00FF
Reserved 128M - 256 3400 0100 - 3BFF FFFF
L3 ROM 64K 3C00 0000 - 3C00 FFFF
Reserved 16M - 64K 3C01 0000 - 3CFF FFFF
UTOPIA Receive (RX) Data 128 3D00 0000 - 3D00 007F
Reserved 896 3D00 0080 - 3D00 03FF
UTOPIA Transmit (TX) Data 128 3D00 0400 - 3D00 047F
Reserved 304M - 1152 3D00 0480 - 4FFF FFFF
TCP2_A Data 1M 5000 0000 - 500F FFFF
TCP2_B Data 1M 5010 0000 - 501F FFFF
Reserved 126M 5020 0000 - 57FF FFFF
VCP2 Data 64K 5800 0000 - 5800 FFFF
Reserved 384M - 64K 5801 0000 - 6FFF FFFF
EMIFA (EMIF64) Configuration Registers 256 7000 0000 - 7000 00FF
Reserved 128M - 256 7000 0100 - 77FF FFFF
DDR2 EMIF Configuration Registers 256 7800 0000 - 7800 00FF
Reserved 128M - 256 7800 0100 - 7FFF FFFF
Reserved 512M 8000 0000 - 9FFF FFFF
EMIFA CE2 Data -SBSRAM/Async 8M A000 0000 - A07F FFFF
Reserved 256M - 8M A080 0000 - AFFF FFFF
EMIFA CE3 Data -SBSRAM/Async 8M B000 0000 - B07F FFFF
Reserved 256M - 8M B080 0000 - BFFF FFFF
EMIFA CE4 Data -SBSRAM/Async 8M C000 0000 - C07F FFFF
Reserved 256M - 8M C080 0000 - CFFF FFFF
EMIFA CE5 Data -SBSRAM/Async 8M D000 0000 - D07F FFFF
Reserved 256M - 8M D080 0000 - DFFF FFFF
DDR2 EMIF CE0 Data 512M E000 0000 - FFFF FFFF

5.5 Device Configuration

On the C6457 device, certain device configurations like boot mode and endianess, are selected at device power-on reset. The status of the peripherals (enabled/disabled) is determined after device power-on reset. By default, the peripherals on the C6457 device are disabled and need to be enabled by software before being used.

5.5.1 Device Configuration at Device Reset

Table 5-15 describes the C6457 device configuration pins. The logic level is latched at power-on reset to determine the device configuration. The logic level on the device configuration pins can be set by using external pullup/pulldown resistors or by using some control device (e.g., FPGA/CPLD) to intelligently drive these pins. When using a control device, care should be taken to ensure there is no contention on the lines when the device is out of reset. The device configuration pins are sampled during power-on reset and are driven after the reset is removed. To avoid contention, the control device must stop driving the device configuration pins of the DSP.

NOTE

If a configuration pin must be routed out from the device and it is not driven (Hi-Z state), the internal pullup/pulldown (IPU/IPD) resistor should not be relied upon. TI recommends the use of an external pullup/pulldown resistor. For more detailed information on pullup/pulldown resistors and situations in which external pullup/pulldown resistors are required, see Section 5.5.6.

Table 5-15 C6457 Device Configuration Pins

CONFIGURATION PIN NO. IPD/IPU(2) FUNCTIONAL DESCRIPTION
GPIO[0] A5 IPU Device Endian mode (LENDIAN)
  • 0 = Device operates in Big Endian mode.
  • 1 = Device operates in Little Endian mode (default).
GPIO[4:1] [B5, B4, D5, E5] IPD Boot Mode Selection (BOOTMODE [3:0])
  • These pins select the boot mode for the device. For more information on the boot modes, see Section 5.7.2.
GPIO[8:5] [B25, F5, C5, F6] IPD Device Number (DEVNUM[3:0])
GPIO[13:9] [C23, D24, C25, A25, C24] IPD Configuration General-Purpose Inputs (CFGGP[4:0])
  • The value of these pins is latched to the Device Status Register following power-on reset and is used by the software.
GPIO[14] D23 IPD HPI peripheral bus width select (HPIWIDTH)
  • 0 = HPI operates in HPI16 mode (default).
    HPI bus is 16-bits wide; HD[15:0] pins are used and the remaining HD[31:16] pins are reserved pins in the Hi-Z state.
  • 1 = HPI operates in HPI32 mode.
    HPI bus is 32 bits wide; HD[31:0] pins are used.
GPIO[15] F23 IPD EMIFA input clock source select (ECLKINSEL).
  • 0 = ECLKIN (default mode)
  • 1 = SYSCLK7 (CPU/x) Clock Rate.
    The SYSCLK7 clock rate is software selectable via the Software PLL1 Controller. By default, SYSCLK7 is selected as CPU ÷ 10 clock rate.
CORECLKSEL AE6 Core Clock Select
  • 0 = CORECLK(N|P) is the input to main PLL.
  • 1 = ALTCORECLK is used as the input to main PLL.
DDRCLKSEL G6 DDR Clock Select
  • 0 = DDRREFCLK(N|P) is the input to DDR PLL.
  • 1 = ALTDDRCLK is used as the input to DDR PLL.

5.5.2 Peripheral Selection After Device Reset

Several of the peripherals on the C6457 are controlled by the Power Sleep Controller (PSC). By default, the SRIO, TCP2_A, TCP2_B, and VCP are held in reset and clock-gated. The memories in these modules are also in a low-leakage sleep mode. Software is required to turn these memories on. Then, the software enables the modules (turns on clocks and de-asserts reset) before these modules can be used.

In addition, the EMIFA, HPI, and UTOPIA come up clock-gated and held in reset. Memories in these modules are already enabled. Software is required to enable these modules before they are used as well.

If one of the above modules is used in the selected ROM boot mode, the ROM code will automatically enable the module.

All other modules come up enabled by default and there is no special software sequence to enable. For more detailed information on the PSC usage, see the TMS320C6457 DSP Power/Sleep Controller PSC User's Guide (SPRUGL4).

5.5.3 Device State Control Registers

The C6457 device has a set of registers that are used to control the status of its peripherals. These registers are shown in Table 5-16 and described in the next sections.

Table 5-16 Device State Control Registers(1)

HEX ADDRESS RANGE ACRONYM DESCRIPTION
0288 0818 JTAGID Parameters for DSP device ID. Also referred to as JTAG or BSDL ID. These are readable by the configuration bus and can be accessed via the JTAG and the CPU.
0288 081C - Reserved
0288 0820 DEVSTAT Stores parameters latched from configuration pins
0288 0824 - 0288 0837 - Reserved
0288 0838 KICK0 Two successive key writes are required to get write access to any of the device state control registers. KICK0 is the first key register. The written data must be 0x83E70B13 to unlock it and it must be written before the KICK1 register. Writing any other value will lock the device state control registers.
0288 083C KICK1 KICK1 is the second key register to be unlocked in order to get write access to any of the device state control registers. The written data must be 0x95A4F1E0 to unlock it and it must be written after the KICK0 register. Writing any other value will lock the device state control registers.
0288 0840 DSP_BOOT
_ADDR		 DSP boot address
0288 0844 - 0288 090F - Reserved
0288 0910 DEVCFG Parameters set through software for device configuration
0288 0914 MACID1 EFUSE derived MAC address for C6457
0288 0918 MACID2 EFUSE derived MAC address for C6457
0288 0922 - 0288 091B - Reserved
0288 091C PRI_ALLOC Sets priority for Master peripherals
0288 0920 WDRSTSEL Reset select for Watchdog (Timer1)
(1) Writes are conditional based on valid keys written to both the KICK0 and KICK1 registers.

5.5.4 Device Status Register Description

The device status register depicts the device configuration selected upon power-on reset. Once set, these bits will remain set until a power-on reset. For the actual register bit names and their associated bit field descriptions, see Figure 5-7 and Table 5-18.

Table 5-17 shows the parameters that are set through software to configure different components on the device. The configuration is done through the device configuration DEVCFG register, which is one-time writeable through software. The register is reset on all hard resets and is locked after the first write.

Table 5-17 Device Configuration Register Fields

FIELD RESET DESCRIPTION SETTINGS
Device Configuration 1 Register Fields
CLKS0 0b McBSP0 CLKS Select
  • 0 = CLKS0 device pin
  • 1 = chip_clks from Main.PLL
CLKS1 0b McBSP1 CLKS Select
  • 0 = CLKS1 device pin
  • 1 = chip_clks from Main.PLL
SYSCLKOUTEN 1b SYSCLKOUT Enable
  • 0 = No clock output
  • 1 = Clock output enabled
Figure 5-7 Device Configuration Status Register (DEVSTAT) (HEX ADDRESS - 0288 0820h)(1)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
R-0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ECLKINSEL HPIWIDTH CFGGP DEVNUM BOOTMODE LENDIAN
0 0 R-n R R R-1
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 5-18 Device Configuration Status Register Field Descriptions

Bit Acronym Description
31:16 Reserved Reserved. Read only, writes have no effect.
15 ECLKINSEL EMIFA input clock select — shows the status of what clock mode is enabled or disabled for EMIFA.
  • 0 = ECLKIN (default mode)
  • 1 = SYSCLK7 (CPU ÷ x) Clock Rate. The SYSCLK7 clock rate is software selectable via the PLL1 Controller. By default, SYSCLK7 is selected as CPU ÷ 10 clock rate.
14 HPIWIDTH HPI bus width control bit — shows the status of whether the HPI bus operates in 32-bit mode or in 16-bit mode.
  • 0 = HPI operates in 16-bit mode. (default)
  • 1 = HPI operates in 32-bit mode
13:9 CFGGP[4:0] Used as general-purpose inputs for configuration purposes. These pins are latched at power-on reset. These values can be used by software routines for boot operations.
8:5 DEVNUM[3:0] Device number.
4:1 BOOTMODE[3:0] Determines the boot method for the device. For more information on bootmode, see Section 5.7.2.
  • 0000 = No Boot
  • 0001 = I2C Master Boot (Slave Address 0x50)
  • 0010 = I2C Master Boot (Slave Address 0x51)
  • 0011 = I2C Slave Boot
  • 0100 = HPI Boot
  • 0101 = EMIFA Boot
  • 0110 = EMAC Master Boot
  • 0111 = EMAC Slave Boot
  • 1000 = EMAC Forced Mode Boot
  • 1001 = Reserved
  • 1010 = RapidIO Boot (Configuration 0)
  • 1011 = RapidIO Boot (Configuration 1)
  • 1100 = RapidIO Boot (Configuration 2)
  • 1101 = RapidIO Boot (Configuration 3)
  • 111x = Reserved
0 LENDIAN Device Endian mode (LENDIAN) — Shows the status of whether the system is operating in Big Endian mode or Little Endian mode (default).

0 = System is operating in Big Endian mode

1 = System is operating in Little Endian mode (default)

5.5.5 JTAG ID (JTAGID) Register Description

The JTAG ID register is a read-only register that identifies to the customer the JTAG/Device ID. For the C6457 device, the JTAG ID register resides at address location 0x0288 0818. For the actual register bit names and their associated bit field descriptions, see Figure 5-8 and Table 5-19.

Figure 5-8 JTAG ID (JTAGID) Register (HEX ADDRESS - 0288 0818h)(1)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
VARIANT PART NUMBER (16-bit)
R-0000
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PART NUMBER (Continued) MANUFACTURER LSB
R-0000 0000 1001 0110b 0000 0010 111b R-1
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 5-19 JTAG ID (JTAGID) Register Field Descriptions

Bit Acronym Value Description
31:28 VARIANT 0000 Variant (4-Bit) value. The value of this field depends on the silicon revision being used.
27:12 PART NUMBER 0000 0000 1001 0110b Part Number for boundary scan
11:1 MANUFACTURER 0000 0010 111b Manufacturer
0 LSB 1b This bit is read as a 1 for C6457

5.5.6 Pullup/Pulldown Resistors

Proper board design should ensure that input pins to the C6457 device always be at a valid logic level and not floating. This may be achieved via pullup/pulldown resistors. The C6457 device features internal pullup (IPU) and internal pulldown (IPD) resistors on most pins to eliminate the need, unless otherwise noted, for external pullup/pulldown resistors.

An external pullup/pulldown resistor needs to be used in the following situations:

  • Device Configuration Pins: If the pin is both routed out and are not driven (in Hi-Z state), an external pullup/pulldown resistor must be used, even if the IPU/IPD matches the desired value/state.
  • Other Input Pins: If the IPU/IPD does not match the desired value/state, use an external pullup/pulldown resistor to pull the signal to the opposite rail.

For the device configuration pins (listed in Table 5-15), if they are both routed out and are not driven (in Hi-Z state), it is strongly recommended that an external pullup/pulldown resistor be implemented. Although, internal pullup/pulldown resistors exist on these pins and they may match the desired configuration value, providing external connectivity can help ensure that valid logic levels are latched on these device configuration pins. In addition, applying external pullup/pulldown resistors on the device configuration pins adds convenience to the user in debugging and flexibility in switching operating modes.

Tips for choosing an external pullup/pulldown resistor:

  • Consider the total amount of current that may pass through the pullup or pulldown resistor. Make sure to include the leakage currents of all the devices connected to the net, as well as any internal pullup or pulldown resistors.
  • Decide a target value for the net. For a pulldown resistor, this should be below the lowest VIL level of all inputs connected to the net. For a pullup resistor, this should be above the highest VIH level of all inputs on the net. A reasonable choice would be to target the VOL or VOH levels for the logic family of the limiting device; which, by definition, have margin to the VIL and VIH levels.
  • Select a pullup/pulldown resistor with the largest possible value that can still ensure that the net will reach the target pulled value when maximum current from all devices on the net is flowing through the resistor. The current to be considered includes leakage current plus, any other internal and external pullup/pulldown resistors on the net.
  • For bidirectional nets, there is an additional consideration that sets a lower limit on the resistance value of the external resistor. Verify that the resistance is small enough that the weakest output buffer can drive the net to the opposite logic level (including margin).
  • Remember to include tolerances when selecting the resistor value.
  • For pullup resistors, also remember to include tolerances on the DVDD rail.

For most systems:

  • A 1-kΩ resistor can be used to oppose the IPU/IPD while meeting the above criteria. Users should confirm this resistor value is correct for their specific application.
  • A 20-kΩ resistor can be used to compliment the IPU/IPD on the device configuration pins while meeting the above criteria. Users should confirm this resistor value is correct for their specific application.

For more detailed information on input current (II), and the low-level/high-level input voltages (VIL and VIH) for the C6457 device, see Section 4.4.

To determine which pins on the C6457 device include internal pullup/pulldown resistors, see Table 3-2.

5.6 System Interconnect

On the C6457 device, the C64x+ Megamodule, the EDMA3 transfer controllers, and the system peripherals are interconnected through two switch fabrics. The switch fabrics allow for low-latency, concurrent data transfers between master peripherals and slave peripherals; for example, through a switch fabric the CPU can send data to the Viterbi co-processor (VCP2) without affecting a data transfer between the HPI and the DDR2 memory controller. The switch fabrics also allow for seamless arbitration between the system masters when accessing system slaves.

5.6.1 Internal Buses, Bridges, and Switch Fabrics

Two types of buses exist in the C6457 device: data buses and configuration buses. Some C6457 peripherals have both a data bus and a configuration bus interface, while others only have one type of interface. Furthermore, the bus interface width and speed varies from peripheral to peripheral. Configuration buses are mainly used to access the register space of a peripheral and the data buses are used mainly for data transfers. However, in some cases, the configuration bus is also used to transfer data. For example, data is transferred to the VCP2 and TCP2 via their configuration bus. Similarly, the data bus can also be used to access the register space of a peripheral. For example, the EMIFA and DDR2 memory controller registers are accessed through their data bus interface.

The C64x+ Megamodule, the EDMA3 traffic controllers, and the various system peripherals can be classified into two categories: masters and slaves.

Masters are capable of initiating read and write transfers in the system and do not rely on the EDMA3 for their data transfers. Slaves on the other hand rely on the EDMA3 to perform transfers to and from them. Examples of masters include the EDMA3 traffic controllers, SRIO, EMAC, and HPI. Examples of slaves include the McBSP, UTOPIA, and I2C.

The C6457 device contains two switch fabrics through which masters and slaves communicate. The data switch fabric, known as the data switched central resource (SCR), is a high-throughput interconnect mainly used to move data across the system (for more information, see Section 5.6.2). The data SCR connects masters to slaves via 128-bit data buses running at a SYSCLK4 frequency (SYSCLK4 is generated from PLL controller). Peripherals that have a 128-bit data bus interface running at this speed can connect directly to the data SCR; other peripherals require a bridge.

The configuration switch fabric, also known as the configuration switch central resource (SCR), is mainly used by the C64x+ Megamodule to access peripheral registers (for more information, see Section 5.6.3). The configuration SCR connects C64x+ Megamodule to slaves via 32-bit configuration buses running at a SYSCLK4 frequency (SYSCLK4 is generated from PLL controller). As with the data SCR, some peripherals require the use of a bridge to interface to the configuration SCR. Note that the data SCR also connects to the configuration SCR.

Bridges perform a variety of functions:

  • Conversion between configuration bus and data bus.
  • Width conversion between peripheral bus width and SCR bus width.
  • Frequency conversion between peripheral bus frequency and SCR bus frequency.

For example, the EMIFA requires a bridge to convert its 64-bit data bus interface into a 128-bit interface so that it can connect to the data SCR. In the case of the TCP2 and VCP2, a bridge is required to connect the data SCR to the 64-bit configuration bus interface.

Note that some peripherals can be accessed through the data SCR and also through the configuration SCR.

5.6.2 Data Switch Fabric Connections

Figure 5-9 shows the connection between slaves and masters through the data switched central resource (SCR). Masters are shown on the left and slaves on the right. The data SCR connects masters to slaves via 128-bit data buses running at a SYSCLK4 frequency. SYSCLK4 is supplied by the PLL controller and is fixed at a frequency equal to the CPU frequency divided by 3.

SM320C6457-HIREL Data_Switched_Central_Resource_Block_Diagram_6484.gif Figure 5-9 Data Switched Central Resource Block Diagram

Masters are shown on the left and slaves on the right. The data SCR connects masters to slaves via 128-bit data buses running at a SYSCLK4 frequency. SYSCLK4 is supplied by the PLL controller and is fixed at a frequency equal to the CPU frequency divided by 3.

Some peripherals and the C64x+ Megamodule have both slave and master ports. Note that each EDMA3 transfer controller has an independent connection to the data SCR.

The Serial RapidIO (SRIO) peripheral has two connections to the data SCR. The first connection is used when descriptors are being fetched from system memory. The other connection is used for all other data transfers.

Note that masters can access the configuration SCR through the data SCR. The configuration SCR is described in Section 5.6.3.

Not all masters on the C6457 DSP may connect to all slaves. Allowed connections are summarized in Table 5-20.

Table 5-20 SCR Connection Matrix

VCP2 TCP2_A TCP2_B McBSPs L3 ROM UTOPIA CONFIGURATION SCR DDR2 MEMORY CONTROLLER EMIFA MEGAMODULE
TC0 Y Y Y N N N N Y Y Y
TC1 N N Y Y Y N N Y Y Y
TC2 N N N Y Y Y Y Y Y Y
TC3 N N N N N Y Y Y Y Y
TC4 N N N N N N Y Y Y Y
TC5 N N N N N N Y Y Y Y
EMAC N N N N N N N Y Y Y
HPI N N N N N N Y Y Y Y
SRIO(1) N N N N N N Y Y Y Y
MEGAMODULE Y Y Y Y Y Y N Y Y N
(1) Applies to both descriptor and data accesses by the SRIO peripheral.

5.6.3 Configuration Switch Fabric

Figure 5-10 shows the connection between the C64x+ Megamodule and the configuration switched central resource (SCR). The configuration SCR is mainly used by the C64x+ Megamodule to access peripheral registers. The data SCR also has a connection to the configuration SCR which allows masters to access most peripheral registers. The only registers not accessible by the data SCR through the configuration SCR are the device configuration registers and the PLL controller registers; these can only be accessed by the C64x+ Megamodule.

The configuration SCR uses 32-bit configuration buses running at SYSCLK4 frequency. SYSCLK4 is supplied by the PLL controller and is fixed at a frequency equal to the CPU frequency divided by 3.

SM320C6457-HIREL Configuration_Switched_Central_Resource_Block_Diagram_6484.gif Figure 5-10 Configuration Switched Central Resource (SCR) Block Diagram

5.6.4 Bus Priorities

On the C6457 device, bus priority is programmable for each master. The register bit fields and default priority levels for C6457 bus masters are shown in Table 5-21.

Table 5-21 C6457 Default Bus Master Priorities

BUS MASTER DEFAULT PRIORITY LEVEL PRIORITY CONTROL
EDMA3TC0 0 QUEPRI.PRIQ0 (EDMA3 register)
EDMA3TC1 0 QUEPRI.PRIQ1 (EDMA3 register)
EDMA3TC2 0 QUEPRI.PRIQ2 (EDMA3 register)
EDMA3TC3 0 QUEPRI.PRIQ3 (EDMA3 register)
EDMA3TC4 0 QUEPRI.PRIQ4 (EDMA3 register)
EDMA3TC5 0 QUEPRI.PRIQ5 (EDMA3 register)
EMAC 1 PRI_ALLOC.EMAC
SRIO (Data Access) 0 PER_SET_CNTL.CBA_TRANS_PRI (SRIO register)
SRIO (Descriptor Access) 1 PRI_ALLOC.SRIO_CPPI
HPI 2 PRI_ALLOC.HOST
C64x+ Megamodule (MDMA port) 7 MDMAARBE.PRI (C64x+ Megamodule Register)

The priority levels should be tuned to obtain the best system performance for a particular application. Lower values indicate higher priorities. For some masters, the priority values are programmed at the system level by configuring the PRI_ALLOC register. Details on the PRI_ALLOC register are shown in Figure 5-11 and Table 5-22. The C64x+ megamodule, SRIO, and EDMA masters contain registers that control their own priority values.

Figure 5-11 Priority Allocation Register (PRI_ALLOC) (0x0288 091C)(2)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
R-0000 0000 0000 0000
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved HPI SRIO_CPPI EMAC
R-0000 000 R/W-010 R/W-001 R/W-001
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 5-22 Priority Allocation Register (PRI_ALLOC) Field Descriptions

Bit Acronym Value Description
31:16 Reserved 0000 0000 0000 0000 Reserved.
15:9 Reserved 0000 000 Reserved.
8:6 HOST 010 Priority of the HPI peripheral.
5:3 SRIO_CPPI 001 Priority of the Serial RapidIO when accessing descriptors from system memory. This priority is set in the peripheral, itself.
2:0 EMAC 001 Priority of the EMAC peripheral.

The priority is enforced when several masters in the system are vying for the same endpoint. Note that the configuration SCR port on the data SCR is considered a single endpoint meaning priority will be enforced when multiple masters try to access the configuration SCR. Priority is also enforced on the configuration SCR side when a master (through the data SCR) tries to access the same endpoint as the C64x+ megamodule.

In the PRI_ALLOC register, the HOST field applies to the priority of the HPI peripheral. The EMAC fields specify the priority of the EMAC peripheral. The SRIO_CPPI field is used to specify the priority of the Serial RapidIO when accessing descriptors from system memory. The priority for Serial RapidIO data accesses is set in the peripheral itself.

5.7 Boot Modes

The device supports several boot processes, which leverage the internal boot ROM. Most boot processes are software driven, using the BOOTMODE[3:0] device configuration inputs to determine the software configuration that must be completed. From a hardware perspective, there are two possible boot modes:

  • Public ROM Boot - C64x+ Megamodule is released from reset and begins executing from the L3 ROM base address. After performing the boot process (e.g., from I2C ROM, Ethernet, or RapidIO), the C64x+ Megamodule then begins execution from the L2 RAM base address.
  • Secure ROM Boot - On secure devices, the C64x+ Megamodule is released from reset and begin executing from secure ROM. Software in the secure ROM will free up internal RAM pages, after which the C64x+ Megamodule initiates the boot process. The C64x+ Megamodule performs any authentication and decryption required on the bootloaded image prior to beginning execution.

The boot process performed by the C64x+ Megamodule in public ROM boot and secure ROM boot are determined by the BOOTMODE[3:0] value in the DEVSTAT register. The C64x+ Megamodule reads this value, and then executes the associated boot process in software. Table 5-23 shows the supported boot modes.

Table 5-23 SM320C6457-HIREL Supported Boot Modes

MODE NAME BOOTMODE[3:0] DESCRIPTION
No Boot 0000b No Boot
I2C Master Boot A 0001b Slave I2C address is 0x50. The C64x+ Megamodule configures I2C, acts as a master to the I2C bus and copies data from an I2C EEPROM or a device acting as an I2C slave to the DSP using a predefined boot table format. The destination address and length are contained within the boot table.
I2C Master Boot B 0010b Similar to I2C boot A except the slave I2C address is 0x51.
I2C Slave Boot 0011b The C64x+ Megamodule configures I2C and acts as a slave and will accept data and code section packets through the I2C interface. It is required that an I2C master is present in the system.
HPI Boot 0100b Host boot.
EMIFA Boot 0101b External memory boot from ACE3 space (0xB0000000 address).
EMAC Master Boot 0110b TI Ethernet Boot. The C64x+ Megamodule configures EMAC and EDMA, if required, and brings the code image into the internal on-chip memory via the protocol defined by the boot method (EMAC bootloader).
EMAC Slave Boot 0111b
EMAC Forced-Mode Boot 1000b
Reserved 1001b Reserved
RapidIO Boot
(Config 0)		 1010b The C64x+ Megamodule configures the SRIO and an external host loads the application via SRIO peripheral, using directIO protocol. A doorbell interrupt is used to indicate that the code has been loaded. For more details on the RapidIO configurations, see Table 5-24.
RapidIO Boot
(Config 1)		 1011b
RapidIO Boot
(Config 2)		 1100b
RapidIO Boot
(Config 3)		 1101b

The C64x+ Megamodule configures Serial RapidIO, EMAC, and EDMA, if required, and brings the code image into the internal on-chip memory via the protocol defined by the boot method (SRIO EMAC bootloader).

Table 5-24 Serial RapidIO (SRIO) Supported Boot Modes

SRIO BOOT MODE SERDES CLOCK LINK RATE SRIO BOOT CONFIGURATION
Bootmode 10 - Config 0 125 MHz 1.25 Gbps Four 1× SRIO links
Bootmode 11 - Config 1 125 MHz 3.125 Gbps One 4× SRIO link
Bootmode 12 - Config 2 156.25 MHz 1.25 Gbps One 4× SRIO link
Bootmode 13 - Config 3 156.25 MHz 3.125 Gbps One 4× SRIO link

All the other BOOTMODE[3:0] modes are reserved.

5.7.1 Second-Level Bootloaders

Any of the boot modes can be used to download a second-level bootloader. A second-level bootloader allows for any level of customization to current boot methods as well as the definition of a completely customized boot.

5.7.2 Boot Sequence

The boot sequence is a process by which the DSP's internal memory is loaded with program and data sections. The DSP's internal registers are programmed with predetermined values. The boot sequence is started automatically after each power-on reset, warm reset, and system reset. A local reset to an individual C64x+ Megamodule should not affect the state of the hardware boot controller on the device. For more details on the initiators of the resets, see Section 4.7.3.

The SM320C6457-HIREL supports several boot processes begins execution at the ROM base address, which contains the bootloader code necessary to support various device boot modes. The boot processes are software driven; using the BOOTMODE[3:0] device configuration inputs to determine the software configuration that must be completed.

5.8 Rake Search Accelerator (RSA)

On the C6457 device, there are two Rake Search Accelerators (RSAs). These RSAs are connected directly to the C64x+ CPU. The RSA is an extension of the C64x+ CPU. The CPU performs send/receive to the RSAs via the .L and .S functional units.