JAJSEA4A September   2017  – December 2017 SN55HVD233-SP

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      概略回路図
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Driver Electrical Characteristics
    6. 7.6  Receiver Electrical Characteristics
    7. 7.7  Driver Switching Characteristics
    8. 7.8  Receiver Switching Characteristics
    9. 7.9  Device Switching Characteristics
    10. 7.10 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Modes
      2. 9.3.2 Loopback
      3. 9.3.3 CAN Bus States
      4. 9.3.4 ISO 11898 Compliance of SN55HVD233-SP
        1. 9.3.4.1 Introduction
        2. 9.3.4.2 Differential Signal
          1. 9.3.4.2.1 Common-Mode Signal
        3. 9.3.4.3 Interoperability of 3.3-V CAN in 5-V CAN Systems
      5. 9.3.5 Thermal Shutdown
    4. 9.4 Device Functional Modes
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Diagnostic Loopback
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Slope Control
        2. 10.2.2.2 Standby
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 Bus Loading, Length, and Number of Nodes
      2. 12.1.2 CAN Termination
    2. 12.2 Layout Example
  13. 13デバイスおよびドキュメントのサポート
    1. 13.1 ドキュメントの更新通知を受け取る方法
    2. 13.2 コミュニティ・リソース
    3. 13.3 商標
    4. 13.4 静電気放電に関する注意事項
    5. 13.5 Glossary
  14. 14メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.6 Receiver Electrical Characteristics

The specifications shown below are valid across temperature range of –55°C to 125°C pre-radiation and 25°C post-radiation. When different, the post-radiation values are shown in a separate row specified by the corresponding RHA level (L = 50 krad).
PARAMETERTEST CONDITIONSSUBGROUP(2)MINTYP(1)MAXUNIT
VIT+ Positive-going input threshold voltage V(LBK) = 0 V, see Table 2 [1, 2, 3] 750 900 mV
VIT– Negative-going input threshold voltage [1, 2, 3] 500 650 mV
Vhys Hysteresis voltage (VIT+ – VIT–) 100 mV
VOH High-level output voltage IO = –4 mA, see Figure 17 [1, 2, 3] 2.4 V
VOL Low-level output voltage IO = 4 mA, see Figure 17 [1, 2, 3] 0.4 V
II Bus input current V(CANH) or V(CANL) = 12 V Other bus pin = 0 V,
V(D) = 3 V,
V(LBK) = 0 V,
V(RS) = 0 V		 [1, 2, 3] 150 500 μA
V(CANH) or V(CANL) = 12 V,
VCC = 0 V		 [1, 2, 3] 150 600
CANH or CANL = –7 V [1, 2, 3] –610 –100
CANH or CANL = –7 V,
VCC = 0 V		 [1, 2, 3] –450 –100
CI Input capacitance (CANH or CANL) Pin-to-ground, VI = 0.4 sin(4E6πt) + 0.5 V,
V(D) = 3 V, V(LBK) = 0 V		 40 pF
CID Differential input capacitance Pin-to-pin, VI = 0.4 sin(4E6πt) + 0.5 V,
V(D) = 3 V, V(LBK) = 0 V 		20 pF
RID Differential input resistance V(D) = 3 V, V(LBK) = 0 V [4, 5, 6] 40 105 kΩ
RIN Input resistance (CANH or CANL) [4, 5, 6] 20 55 kΩ
ICC Supply current Standby V(RS) = VCC, V(D) = VCC, V(LBK) = 0 V [1, 2, 3] 200 600 μA
Dominant V(D) = 0 V, no load, V(RS) = 0 V, V(LBK) = 0 V [1, 2, 3] 6 mA
Recessive V(D) = VCC, no load, V(RS) = 0 V, V(LBK) = 0 V [1, 2, 3] 6 mA
(1) All typical values are at 25°C and with a 3.3-V supply.
(2) For subgroup definitions, please see Table 1.