JAJSGH0D november   2018  – october 2020 SN6505A-Q1 , SN6505B-Q1 , SN6505D-Q1

PRODUCTION DATA  

  1.   1
  2. 特長
  3. アプリケーション
  4. 概要
  5. Revision History
  6. Pin Configuration and Functions
  7. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics, SN6505A-Q1
    8. 6.8 Typical Characteristics, SN6505B-Q1 or SN6505D-Q1
  8. Parameter Measurement Information
  9. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Push-Pull Converter
      2. 8.3.2 Core Magnetization
    4. 8.4 Device Functional Modes
      1. 8.4.1 Start-Up Mode
        1. 8.4.1.1 Soft-Start
      2. 8.4.2 Operating Mode
      3. 8.4.3 Shutdown-Mode
      4. 8.4.4 Spread Spectrum Clocking
      5. 8.4.5 External Clock Mode
  10. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Drive Capability
        2. 9.2.2.2 LDO Selection
        3. 9.2.2.3 Diode Selection
        4. 9.2.2.4 Capacitor Selection
        5. 9.2.2.5 Transformer Selection
          1. 9.2.2.5.1 V-t Product Calculation
          2. 9.2.2.5.2 Turns Ratio Estimate
          3. 9.2.2.5.3 Recommended Transformers
      3. 9.2.3 Application Curves
      4. 9.2.4 System Examples
        1. 9.2.4.1 Higher Output Voltage Designs
        2. 9.2.4.2 Application Circuits
  11. 10Power Supply Recommendations
  12. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  13. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 サード・パーティ製品に関する免責事項
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Related Links
    4. 12.4 ドキュメントの更新通知を受け取る方法
    5. 12.5 サポート・リソース
    6. 12.6 Trademarks
    7. 12.7 静電気放電に関する注意事項
    8. 12.8 用語集
  14. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報
Recommended Transformers

Depending on the application, use the minimum configuration in Figure 9-7 or standard configuration in Figure 9-8.

GUID-33FB7F8A-AA58-490A-8B73-12C7A8BBDE55-low.pngFigure 9-7 Unregulated Output for Low-Current Loads With Wide Supply Range
GUID-3919477D-16BA-4B26-8288-7648CBFB8CD1-low.pngFigure 9-8 Regulated Output for Stable Supplies and High Current Loads

The Wurth Electronics Midcom isolation transformers in Table 9-3 are optimized designs for the device, providing high efficiency and small form factor at low-cost.

The 1:1.1 and 1:1.7 turns-ratios are designed for logic applications with wide supply rails and low load currents. These applications operate without LDO, thus achieving further cost-reduction.

Table 9-3 Recommended Isolation Transformers Optimized for the Device
TURNS
RATIO
V × T
(Vμs)
ISOLATION
(VRMS)
DIMENSIONS
(mm)
APPLICATIONLDO(1)ORDER NO.MANUFACTURER
1:1.1 ±2%725006.73 x 10.05 x 4.193.3 V → 3.3 V, 100mA, SN6505B/D-Q1
Refer to Figure 6-13 and Figure 6-14
No760390011Wurth Electronics / Midcom
1:1.1 ±2%115 V → 5 V, 100mA, SN6505B/D-Q1
Refer to Figure 6-15 and Figure 6-16
760390012
1:1.7 ±2%3.3 V → 5 V, 100mA, SN6505B/D-Q1
Refer to Figure 6-17 and Figure 6-18
760390013
1:1.3 ±2%3.3 V → 3.3 V, 100mA, SN6505B/D-Q1
Refer to Figure 6-19 and Figure 6-20
Yes760390014
1:1.3 ±2%5 V → 5 V, 100mA, SN6505B/D-Q1
Refer to Figure 6-21 and Figure 6-22
760390014
1:2.1 ±2%3.3 V → 5 V, 100mA, SN6505B/D-Q1
Refer to Figure 6-23 and Figure 6-24
760390015
1.23:1 ±2%5 V → 3.3 V, 100mA, SN6505B/D-Q1750313710
1:1.7 ±2%8.98.3 x 12.6 x 4.13.3 V → 3.3 V, 1A, SN6505B/D-Q1
Refer to Figure 6-25 and Figure 6-26
750316028
1:2.1 ±2%3.3 V → 5 V, 1A, SN6505B/D-Q1
Refer to Figure 6-27 and Figure 6-28
No750316029
1.3:1 ±2%10.85 V → 3.3 V, 1A, SN6505B/D-Q1
Refer to Figure 6-29 and Figure 6-30
750316030
1:1.1 ±2%8.63.3 V → 3.3 V , 1A , SN6505B/D-Q1
5 V → 5 V , 1A , SN6505B/D-Q1
Refer to Figure 6-11 and Figure 6-12
750315371
1:1.1 ±2%1150009.14 x 12.7 x 7.373.3 V → 3.3 V, 100mA, SN6505B/D-Q1750313734
1:1.1 ±2%5 V → 5 V, 100mA, SN6505B/D-Q1750313734
1:1.7 ±2%3.3 V → 5 V, 100mA, SN6505B/D-Q1750313769
1:1.3 ±2%3.3 V → 3.3 V, 100mA, SN6505B/D-Q1
5 V → 5 V, 100mA, SN6505B/D-Q1
Yes750313638
1:2.1 ±2%3.3 V → 5 V, 100mA, SN6505B/D-Q1750313626
1.3:1 ±2%5 V → 3.3 V, 100mA , SN6505B/D-Q1No750313638
1:1.75 ±2%4112.32 x 15.41 x 11.053.3 V → 3.3 V, 1A, SN6505A-Q1
Refer to Figure 6-3 and Figure 6-4
Yes750316031
1:2 ±2%3.3 V → 5 V, 1A, SN6505A-Q1
Refer to Figure 6-5 and Figure 6-6
No750316032
1.3:1 ±2%425.0 V → 3.3 V, 1A, SN6505A-Q1
Refer to Figure 6-7 and Figure 6-8
750316033
1:1.1 ±2%2312.32 x 15.41 x 11.893.3 V → 3.3 V, 1A, SN6505A-Q1
5 V → 5 V, 1A , SN6505A-Q1
Refer to Figure 6-1 and Figure 6-2
750315240
1:1.3 ±3%11500010.4 x 12.2 x 6.13.3 V → 3.3 V, 300mA, SN6505B/D-Q1
5 V → 5 V, 300mA , SN6505B/D-Q1
NoHCT-SM-1.3-8-2Bourns
1:1.5 ±3%34.4250010 x 12.07 x 5.973.3 V → 3.3 V, 1A, SN6505A/B/D-Q1
5 V → 5 V, 1A , SN6505A/B/D-Q1
YesDA2303-ALCoilcraft
1:2.2 ±3%21.5250010 x 12.07 x 5.973.3 V → 5 V, 1A, SN6505A/B/D-Q1DA2304-AL
For configurations with LDO, a higher voltage than the required output voltage is generated, to allow for LDO drop-out. Figures show the voltage and efficiency at the LDO input.